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[ARM] Mark Swift MISched model as incomplete

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The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM
target.

Patch by Christof Douma!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250033 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy 2015-10-12 12:49:59 +00:00
parent 7dab7edf06
commit 85125fcdd6
1 changed files with 1 additions and 0 deletions
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lib/Target/ARM/ARMScheduleSwift.td
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@ -43,6 +43,7 @@ def SwiftModel : SchedMachineModel {
let MicroOpBufferSize = 45; // Based on NEON renamed registers.
let LoadLatency = 3;
let MispredictPenalty = 14; // A branch direction mispredict.
let CompleteModel = 0; // FIXME: Remove if all instructions are covered.
}
// Swift predicates.