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Reuse the MO variable instead of recomputing it in RegAllocLocal.

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Keep RegAllocSimple in sync.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-07-09 20:12:26 +00:00
parent 9a06ed9359
commit 85e6815d83
2 changed files with 9 additions and 9 deletions
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2
lib/CodeGen/RegAllocLocal.cpp
View File

@ -839,7 +839,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
DOUT << " Assigning " << TRI->getName(DestPhysReg)
<< " to %reg" << DestVirtReg << "\n";
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
MO.setReg(DestPhysReg); // Assign the output register
}
}

16
lib/CodeGen/RegAllocSimple.cpp
View File

@ -188,12 +188,12 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
MachineOperand &MO = MI->getOperand(i);
if (op.isRegister() && op.getReg() &&
TargetRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
DOUT << "op: " << op << "\n";
if (MO.isRegister() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned virtualReg = (unsigned) MO.getReg();
DOUT << "op: " << MO << "\n";
DOUT << "\t inst[" << i << "]: ";
DEBUG(MI->print(*cerr.stream(), TM));
@ -201,7 +201,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
if (MO.isDef()) {
int TiedOp = Desc.findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
@ -222,8 +222,8 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
Virt2PhysRegMap[virtualReg] = physReg;
}
}
MI->getOperand(i).setReg(physReg);
DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
MO.setReg(physReg);
DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n";
}
}
RegClassIdx.clear();