[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317582 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Florian Hahn 2017-11-07 15:03:11 +00:00
parent 8cec6c4916
commit 861d2963c7
8 changed files with 16 additions and 0 deletions

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@ -26,6 +26,8 @@ def CortexA53Model : SchedMachineModel {
// Specification - Instruction Timings"
// v 1.0 Spreadsheet
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}

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@ -31,6 +31,8 @@ def CortexA57Model : SchedMachineModel {
// experiments and benchmarking data.
let LoopMicroOpBufferSize = 16;
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}
//===----------------------------------------------------------------------===//

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@ -18,6 +18,8 @@ def CycloneModel : SchedMachineModel {
let LoadLatency = 4; // Optimistic load latency.
let MispredictPenalty = 16; // 14-19 cycles are typical.
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}
//===----------------------------------------------------------------------===//

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@ -23,6 +23,8 @@ def FalkorModel : SchedMachineModel {
let LoadLatency = 3; // Optimistic load latency.
let MispredictPenalty = 11; // Minimum branch misprediction penalty.
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}
//===----------------------------------------------------------------------===//

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@ -27,6 +27,8 @@ def KryoModel : SchedMachineModel {
// experiments and benchmarking data.
let LoopMicroOpBufferSize = 16;
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}
//===----------------------------------------------------------------------===//

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@ -24,6 +24,8 @@ def ExynosM1Model : SchedMachineModel {
let LoadLatency = 4; // Optimistic load cases.
let MispredictPenalty = 14; // Minimum branch misprediction penalty.
let CompleteModel = 1; // Use the default model otherwise.
list<Predicate> UnsupportedFeatures = [HasSVE];
}
//===----------------------------------------------------------------------===//

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@ -25,6 +25,8 @@ def ThunderXT8XModel : SchedMachineModel {
let MispredictPenalty = 8; // Branch mispredict penalty.
let PostRAScheduler = 1; // Use PostRA scheduler.
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}
// Modeling each pipeline with BufferSize == 0 since T8X is in-order.

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@ -25,6 +25,8 @@ def ThunderX2T99Model : SchedMachineModel {
let LoopMicroOpBufferSize = 32;
let PostRAScheduler = 1; // Using PostRA sched.
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
}
// Define the issue ports.