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[Hexagon] Make MI scheduler check for stalls in previous packet on v60

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Patch by Ikhlas Ajbar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275606 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-07-15 20:16:03 +00:00
parent 2347de17da
commit 866d448f64
2 changed files with 41 additions and 3 deletions
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28
lib/Target/Hexagon/HexagonMachineScheduler.cpp
View File

@ -105,6 +105,11 @@ void HexagonCallMutation::apply(ScheduleDAGInstrs *DAG) {
}
/// Save the last formed packet
void VLIWResourceModel::savePacket() {
OldPacket = Packet;
}
/// Check if scheduling of this SU is possible
/// in the current packet.
/// It is _not_ precise (statefull), it is more like
@ -155,6 +160,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
// Artificially reset state.
if (!SU) {
ResourcesModel->clearResources();
savePacket();
Packet.clear();
TotalPackets++;
return false;
@ -163,6 +169,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
// start a new one.
if (!isResourceAvailable(SU)) {
ResourcesModel->clearResources();
savePacket();
Packet.clear();
TotalPackets++;
startNewCycle = true;
@ -199,6 +206,7 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
// we start fresh.
if (Packet.size() >= SchedModel->getIssueWidth()) {
ResourcesModel->clearResources();
savePacket();
Packet.clear();
TotalPackets++;
startNewCycle = true;
@ -552,6 +560,8 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
if (!SU || SU->isScheduled)
return ResCount;
MachineInstr *Instr = SU->getInstr();
// Forced priority is high.
if (SU->isScheduleHigh)
ResCount += PriorityOne;
@ -596,6 +606,24 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
ResCount -= (Delta.Excess.getUnitInc()*PriorityTwo);
ResCount -= (Delta.CriticalMax.getUnitInc()*PriorityTwo);
auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
auto &QII = *QST.getInstrInfo();
// Give less preference to an instruction that will cause a stall with
// an instruction in the previous packet.
if (QII.isV60VectorInstruction(Instr)) {
// Check for stalls in the previous packet.
if (Q.getID() == TopQID) {
for (auto J : Top.ResourceModel->OldPacket)
if (QII.producesStall(J->getInstr(), Instr))
ResCount -= PriorityOne;
} else {
for (auto J : Bot.ResourceModel->OldPacket)
if (QII.producesStall(Instr, J->getInstr()))
ResCount -= PriorityOne;
}
}
DEBUG(if (verbose) dbgs() << " Total(" << ResCount << ")");
return ResCount;

14
lib/Target/Hexagon/HexagonMachineScheduler.h
View File

@ -52,6 +52,10 @@ class VLIWResourceModel {
/// Total packets created.
unsigned TotalPackets;
public:
/// Save the last formed packet.
std::vector<SUnit*> OldPacket;
public:
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
: SchedModel(SM), TotalPackets(0) {
@ -63,6 +67,8 @@ public:
Packet.resize(SchedModel->getIssueWidth());
Packet.clear();
OldPacket.resize(SchedModel->getIssueWidth());
OldPacket.clear();
ResourcesModel->clearResources();
}
@ -85,7 +91,12 @@ public:
bool isResourceAvailable(SUnit *SU);
bool reserveResources(SUnit *SU);
void savePacket();
unsigned getTotalPackets() const { return TotalPackets; }
bool isInPacket(SUnit *SU) const {
return std::find(Packet.begin(), Packet.end(), SU) != Packet.end();
}
};
/// Extend the standard ScheduleDAGMI to provide more context and override the
@ -99,8 +110,6 @@ public:
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
void schedule() override;
/// Perform platform-specific DAG postprocessing.
void postprocessDAG();
};
/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
@ -166,6 +175,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy {
void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
DAG = dag;
SchedModel = smodel;
IssueCount = 0;
}
bool isTop() const {