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[DAGCombine] Fix for PR37563

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While searching for loads to be narrowed, equal sized loads were not
added to the list, resulting in anyext loads not being converted to
zext loads.

https://bugs.llvm.org/show_bug.cgi?id=35763

Differential Revision: https://reviews.llvm.org/D41628


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sam Parker 2018-01-05 08:47:23 +00:00
parent d84b15b1d9
commit 8681051b9e
3 changed files with 21 additions and 14 deletions
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14
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3842,9 +3842,16 @@ bool DAGCombiner::SearchForAndLoads(SDNode *N,
EVT ExtVT;
if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
isLegalNarrowLoad(Load, ISD::ZEXTLOAD, ExtVT)) {
// Only add this load if we can make it more narrow.
if (ExtVT.bitsLT(Load->getMemoryVT()))
// ZEXTLOAD is already small enough.
if (Load->getExtensionType() == ISD::ZEXTLOAD &&
ExtVT.bitsGE(Load->getMemoryVT()))
continue;
// Use LE to convert equal sized loads to zext.
if (ExtVT.bitsLE(Load->getMemoryVT()))
Loads.insert(Load);
continue;
}
return false;
@ -3899,11 +3906,13 @@ bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
if (Loads.size() == 0)
return false;
DEBUG(dbgs() << "Backwards propagate AND: "; N->dump());
SDValue MaskOp = N->getOperand(1);
// If it exists, fixup the single node we allow in the tree that needs
// masking.
if (FixupNode) {
DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump());
SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
FixupNode->getValueType(0),
SDValue(FixupNode, 0), MaskOp);
@ -3922,6 +3931,7 @@ bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
// Create narrow loads.
for (auto *Load : Loads) {
DEBUG(dbgs() << "Propagate AND back to: "; Load->dump());
SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
SDValue(Load, 0), MaskOp);
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);

14
test/CodeGen/ARM/and-load-combine.ll
View File

@ -852,8 +852,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
; ARM-NEXT: uxtb r2, r2
; ARM-NEXT: and r0, r0, r1
; ARM-NEXT: uxtb r1, r0
; ARM-NEXT: and r1, r0, r1
; ARM-NEXT: mov r0, #0
; ARM-NEXT: cmp r1, r2
; ARM-NEXT: movweq r0, #1
@ -863,8 +862,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
; ARMEB: @ %bb.0: @ %entry
; ARMEB-NEXT: ldrb r0, [r0]
; ARMEB-NEXT: uxtb r2, r2
; ARMEB-NEXT: and r0, r0, r1
; ARMEB-NEXT: uxtb r1, r0
; ARMEB-NEXT: and r1, r0, r1
; ARMEB-NEXT: mov r0, #0
; ARMEB-NEXT: cmp r1, r2
; ARMEB-NEXT: movweq r0, #1
@ -872,9 +870,8 @@ define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
;
; THUMB1-LABEL: test6:
; THUMB1: @ %bb.0: @ %entry
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ands r0, r1
; THUMB1-NEXT: uxtb r3, r0
; THUMB1-NEXT: ldrb r3, [r0]
; THUMB1-NEXT: ands r3, r1
; THUMB1-NEXT: uxtb r2, r2
; THUMB1-NEXT: movs r0, #1
; THUMB1-NEXT: movs r1, #0
@ -889,8 +886,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: uxtb r2, r2
; THUMB2-NEXT: ands r0, r1
; THUMB2-NEXT: uxtb r1, r0
; THUMB2-NEXT: ands r1, r0
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: cmp r1, r2
; THUMB2-NEXT: it eq

7
test/CodeGen/X86/pr37563.ll
View File

@ -10,9 +10,10 @@
define void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzwl z+{{.*}}(%rip), %eax
; CHECK-NEXT: orl {{.*}}(%rip), %eax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
; CHECK-NEXT: movzwl z+{{.*}}(%rip), %ecx
; CHECK-NEXT: orl %eax, %ecx
; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
; CHECK-NEXT: shlq $32, %rcx