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https://github.com/RPCS3/llvm.git
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[FastISel][AArch64] Improve floating-point compare support.
Add support for the last two missing fcmp condition codes: UEQ and ONE. This fixes rdar://problem/18341575. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
1ee1e8bdc2
commit
86bdc1efbe
@ -1830,22 +1830,77 @@ bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
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bool AArch64FastISel::SelectCmp(const Instruction *I) {
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const CmpInst *CI = cast<CmpInst>(I);
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// We may not handle every CC for now.
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AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
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if (CC == AArch64CC::AL)
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return false;
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// Try to optimize or fold the cmp.
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CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
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unsigned ResultReg = 0;
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switch (Predicate) {
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default:
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break;
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case CmpInst::FCMP_FALSE:
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ResultReg = createResultReg(&AArch64::GPR32RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(AArch64::WZR, getKillRegState(true));
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break;
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case CmpInst::FCMP_TRUE:
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ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
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break;
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}
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if (ResultReg) {
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updateValueMap(I, ResultReg);
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return true;
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}
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// Emit the cmp.
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if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
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return false;
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ResultReg = createResultReg(&AArch64::GPR32RegClass);
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// FCMP_UEQ and FCMP_ONE cannot be checked with a single instruction. These
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// condition codes are inverted, because they are used by CSINC.
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static unsigned CondCodeTable[2][2] = {
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{ AArch64CC::NE, AArch64CC::VC },
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{ AArch64CC::PL, AArch64CC::LE }
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};
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unsigned *CondCodes = nullptr;
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switch (Predicate) {
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default:
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break;
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case CmpInst::FCMP_UEQ:
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CondCodes = &CondCodeTable[0][0];
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break;
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case CmpInst::FCMP_ONE:
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CondCodes = &CondCodeTable[1][0];
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break;
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}
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if (CondCodes) {
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unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
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TmpReg1)
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.addReg(AArch64::WZR, getKillRegState(true))
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.addReg(AArch64::WZR, getKillRegState(true))
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.addImm(CondCodes[0]);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
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ResultReg)
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.addReg(TmpReg1, getKillRegState(true))
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.addReg(AArch64::WZR, getKillRegState(true))
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.addImm(CondCodes[1]);
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updateValueMap(I, ResultReg);
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return true;
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}
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// Now set a register based on the comparison.
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AArch64CC::CondCode CC = getCompareCC(Predicate);
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assert((CC != AArch64CC::AL) && "Unexpected condition code.");
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AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
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unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
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ResultReg)
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.addReg(AArch64::WZR)
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.addReg(AArch64::WZR)
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.addReg(AArch64::WZR, getKillRegState(true))
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.addReg(AArch64::WZR, getKillRegState(true))
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.addImm(invertedCC);
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updateValueMap(I, ResultReg);
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@ -1,146 +1,162 @@
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; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
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entry:
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; CHECK-LABEL: @fcmp_float1
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; CHECK: fcmp s0, #0.0
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; CHECK: cset w{{[0-9]+}}, ne
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%cmp = fcmp une float %a, 0.000000e+00
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ret i1 %cmp
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define zeroext i1 @fcmp_float1(float %a) {
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; CHECK-LABEL: fcmp_float1
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; CHECK: fcmp s0, #0.0
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une float %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @fcmp_float2(float %a, float %b) nounwind ssp {
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entry:
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; CHECK-LABEL: @fcmp_float2
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; CHECK: fcmp s0, s1
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; CHECK: cset w{{[0-9]+}}, ne
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%cmp = fcmp une float %a, %b
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ret i1 %cmp
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define zeroext i1 @fcmp_float2(float %a, float %b) {
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; CHECK-LABEL: fcmp_float2
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_double1(double %a) nounwind ssp {
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entry:
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; CHECK-LABEL: @fcmp_double1
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; CHECK: fcmp d0, #0.0
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; CHECK: cset w{{[0-9]+}}, ne
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%cmp = fcmp une double %a, 0.000000e+00
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ret i1 %cmp
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define zeroext i1 @fcmp_double1(double %a) {
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; CHECK-LABEL: fcmp_double1
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; CHECK: fcmp d0, #0.0
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une double %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @fcmp_double2(double %a, double %b) nounwind ssp {
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entry:
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; CHECK-LABEL: @fcmp_double2
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; CHECK: fcmp d0, d1
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; CHECK: cset w{{[0-9]+}}, ne
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%cmp = fcmp une double %a, %b
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ret i1 %cmp
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define zeroext i1 @fcmp_double2(double %a, double %b) {
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; CHECK-LABEL: fcmp_double2
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une double %a, %b
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ret i1 %1
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}
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; Check each fcmp condition
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define float @fcmp_oeq(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_oeq
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; CHECK: fcmp s0, s1
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; CHECK: cset w{{[0-9]+}}, eq
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%cmp = fcmp oeq float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_false(float %a) {
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; CHECK-LABEL: fcmp_false
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; CHECK: mov {{w[0-9]+}}, wzr
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%1 = fcmp ogt float %a, %a
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ret i1 %1
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}
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define float @fcmp_ogt(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_ogt
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; CHECK: fcmp s0, s1
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; CHECK: cset w{{[0-9]+}}, gt
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%cmp = fcmp ogt float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_oeq(float %a, float %b) {
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; CHECK-LABEL: fcmp_oeq
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, eq
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%1 = fcmp oeq float %a, %b
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ret i1 %1
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}
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define float @fcmp_oge(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_oge
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; CHECK: fcmp s0, s1
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; CHECK: cset w{{[0-9]+}}, ge
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%cmp = fcmp oge float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_ogt(float %a, float %b) {
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; CHECK-LABEL: fcmp_ogt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, gt
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%1 = fcmp ogt float %a, %b
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ret i1 %1
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}
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define float @fcmp_olt(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_olt
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; CHECK: fcmp s0, s1
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; CHECK: cset w{{[0-9]+}}, mi
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%cmp = fcmp olt float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_oge(float %a, float %b) {
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; CHECK-LABEL: fcmp_oge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ge
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%1 = fcmp oge float %a, %b
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ret i1 %1
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}
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define float @fcmp_ole(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_ole
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; CHECK: fcmp s0, s1
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; CHECK: cset w{{[0-9]+}}, ls
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%cmp = fcmp ole float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_olt(float %a, float %b) {
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; CHECK-LABEL: fcmp_olt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, mi
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%1 = fcmp olt float %a, %b
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ret i1 %1
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}
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define float @fcmp_ord(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_ord
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, vc
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%cmp = fcmp ord float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_ole(float %a, float %b) {
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; CHECK-LABEL: fcmp_ole
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ls
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%1 = fcmp ole float %a, %b
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ret i1 %1
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}
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define float @fcmp_uno(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_uno
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, vs
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%cmp = fcmp uno float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_one(float %a, float %b) {
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; CHECK-LABEL: fcmp_one
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset [[REG:w[0-9]+]], mi
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; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, le
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%1 = fcmp one float %a, %b
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ret i1 %1
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}
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define float @fcmp_ugt(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_ugt
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, hi
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%cmp = fcmp ugt float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_ord(float %a, float %b) {
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; CHECK-LABEL: fcmp_ord
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, vc
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%1 = fcmp ord float %a, %b
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ret i1 %1
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}
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define float @fcmp_uge(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_uge
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, pl
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%cmp = fcmp uge float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_uno(float %a, float %b) {
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; CHECK-LABEL: fcmp_uno
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%1 = fcmp uno float %a, %b
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ret i1 %1
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}
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define float @fcmp_ult(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_ult
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, lt
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%cmp = fcmp ult float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_ueq(float %a, float %b) {
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; CHECK-LABEL: fcmp_ueq
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
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; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, vc
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%1 = fcmp ueq float %a, %b
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ret i1 %1
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}
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define float @fcmp_ule(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_ule
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, le
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%cmp = fcmp ule float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_ugt(float %a, float %b) {
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; CHECK-LABEL: fcmp_ugt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, hi
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%1 = fcmp ugt float %a, %b
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ret i1 %1
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}
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define float @fcmp_une(float %a, float %b) nounwind ssp {
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; CHECK-LABEL: @fcmp_une
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; CHECK: fcmp s0, s1
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; CHECK: cset {{w[0-9]+}}, ne
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%cmp = fcmp une float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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define zeroext i1 @fcmp_uge(float %a, float %b) {
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; CHECK-LABEL: fcmp_uge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, pl
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%1 = fcmp uge float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ult(float %a, float %b) {
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; CHECK-LABEL: fcmp_ult
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, lt
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%1 = fcmp ult float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ule(float %a, float %b) {
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; CHECK-LABEL: fcmp_ule
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, le
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%1 = fcmp ule float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_une(float %a, float %b) {
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; CHECK-LABEL: fcmp_une
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_true(float %a) {
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; CHECK-LABEL: fcmp_true
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; CHECK: orr {{w[0-9]+}}, wzr, #0x1
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%1 = fcmp ueq float %a, %a
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ret i1 %1
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}
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