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Add support for NEON VLD3-dup instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
2fcda63763
commit
86c6d80a7a
@ -172,6 +172,13 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
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{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 },
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{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 },
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{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4},
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{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4},
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{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2},
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{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2},
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{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8},
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{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8},
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{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 },
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{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 },
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{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 },
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@ -946,6 +953,12 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::VLD2DUPd8Pseudo_UPD:
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case ARM::VLD2DUPd16Pseudo_UPD:
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case ARM::VLD2DUPd32Pseudo_UPD:
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case ARM::VLD3DUPd8Pseudo:
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case ARM::VLD3DUPd16Pseudo:
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case ARM::VLD3DUPd32Pseudo:
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case ARM::VLD3DUPd8Pseudo_UPD:
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case ARM::VLD3DUPd16Pseudo_UPD:
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case ARM::VLD3DUPd32Pseudo_UPD:
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ExpandVLD(MBBI);
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break;
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@ -2361,6 +2361,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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return SelectVLDDup(N, 2, Opcodes);
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}
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case ARMISD::VLD3DUP: {
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unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
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ARM::VLD3DUPd32Pseudo };
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return SelectVLDDup(N, 3, Opcodes);
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}
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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@ -896,6 +896,48 @@ def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
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def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
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// VLD3DUP : Vector Load (single 3-element structure to all lanes)
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class VLD3DUP<bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$Rn), IIC_VLD3dup,
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"vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
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let Rm = 0b1111;
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let Inst{4} = Rn{4};
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}
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def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
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def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
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def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
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def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
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def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
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def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
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// ...with double-spaced registers (not used for codegen):
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def VLD3DUPd8T : VLD3DUP<{0,0,1,?}, "8">;
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def VLD3DUPd16T : VLD3DUP<{0,1,1,?}, "16">;
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def VLD3DUPd32T : VLD3DUP<{1,0,1,?}, "32">;
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// ...with address register writeback:
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class VLD3DUPWB<bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3dupu,
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"vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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}
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def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
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def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
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def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
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def VLD3DUPd8T_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
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def VLD3DUPd16T_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
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def VLD3DUPd32T_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
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def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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// VLD4DUP : Vector Load (single 4-element structure to all lanes)
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// FIXME: Not yet implemented.
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} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
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@ -152,6 +152,8 @@ def IIC_VLD3 : InstrItinClass;
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def IIC_VLD3ln : InstrItinClass;
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def IIC_VLD3u : InstrItinClass;
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def IIC_VLD3lnu : InstrItinClass;
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def IIC_VLD3dup : InstrItinClass;
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def IIC_VLD3dupu : InstrItinClass;
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def IIC_VLD4 : InstrItinClass;
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def IIC_VLD4ln : InstrItinClass;
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def IIC_VLD4u : InstrItinClass;
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@ -559,6 +559,18 @@ def CortexA8Itineraries : ProcessorItineraries<
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InstrStage<5, [A8_LSPipe]>],
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[4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
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//
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// VLD3dup
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InstrItinData<IIC_VLD3dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<3, [A8_NLSPipe], 0>,
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InstrStage<3, [A8_LSPipe]>],
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[2, 2, 3, 1]>,
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//
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// VLD3dupu
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InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<3, [A8_NLSPipe], 0>,
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InstrStage<3, [A8_LSPipe]>],
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[2, 2, 3, 2, 1, 1]>,
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//
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// VLD4
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InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrStage<4, [A8_NLSPipe], 0>,
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@ -941,6 +941,24 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<5, [A9_LSUnit]>],
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[5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
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//
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// VLD3dup
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InstrItinData<IIC_VLD3dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_MUX0], 0>,
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InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<3, [A9_NPipe], 0>,
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InstrStage<3, [A9_LSUnit]>],
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[3, 3, 4, 1]>,
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//
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// VLD3dupu
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InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_MUX0], 0>,
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InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<3, [A9_NPipe], 0>,
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InstrStage<3, [A9_LSUnit]>],
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[3, 3, 4, 2, 1, 1]>,
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//
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// VLD4
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InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_MUX0], 0>,
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@ -71,3 +71,23 @@ define <2 x i32> @vld2dupi32(i32* %A) nounwind {
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declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
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declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
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%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
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define <4 x i16> @vld3dupi16(i16* %A) nounwind {
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;CHECK: vld3dupi16:
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;Check the (default) alignment value. VLD3 does not support alignment.
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;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
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%tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
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%tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
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%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 1
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%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
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%tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 2
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%tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer
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%tmp7 = add <4 x i16> %tmp2, %tmp4
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%tmp8 = add <4 x i16> %tmp7, %tmp6
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ret <4 x i16> %tmp8
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}
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
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