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ARM64: hexify printing various immediate operands

Browse Source 
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-30 11:19:28 +00:00
parent 2a2cce79be
commit 87476b607c
14 changed files with 167 additions and 158 deletions
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3
lib/Target/ARM64/ARM64InstrFormats.td
View File

@ -222,6 +222,7 @@ def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 65536;
}]> {
let ParserMatchClass = Imm0_65535Operand;
let PrintMethod = "printHexImm";
}
def Imm1_8Operand : AsmOperandClass {
@ -452,6 +453,7 @@ def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 256;
}]> {
let ParserMatchClass = Imm0_255Operand;
let PrintMethod = "printHexImm";
}
// imm0_127 predicate - True if the immediate is in the range [0,127]
@ -460,6 +462,7 @@ def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 128;
}]> {
let ParserMatchClass = Imm0_127Operand;
let PrintMethod = "printHexImm";
}
// NOTE: These imm0_N operands have to be of type i64 because i64 is the size

6
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
View File

@ -1008,6 +1008,12 @@ void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
}
void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
O << format("#%#llx", Op.getImm());
}
void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
unsigned Imm, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);

1
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
View File

@ -44,6 +44,7 @@ protected:
bool printSysAlias(const MCInst *MI, raw_ostream &O);
// Operand printers
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
raw_ostream &O);
void printPostIncOperand1(const MCInst *MI, unsigned OpNo, raw_ostream &O);

4
test/CodeGen/ARM64/aarch64-neon-copy.ll
View File

@ -1369,7 +1369,7 @@ define <4 x i16> @concat_vector_v4i16_const() {
define <4 x i16> @concat_vector_v4i16_const_one() {
; CHECK-LABEL: concat_vector_v4i16_const_one:
; CHECK: movi {{v[0-9]+}}.4h, #1
; CHECK: movi {{v[0-9]+}}.4h, #0x1
%r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %r
}
@ -1397,7 +1397,7 @@ define <8 x i16> @concat_vector_v8i16_const() {
define <8 x i16> @concat_vector_v8i16_const_one() {
; CHECK-LABEL: concat_vector_v8i16_const_one:
; CHECK: movi {{v[0-9]+}}.8h, #1
; CHECK: movi {{v[0-9]+}}.8h, #0x1
%r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %r
}

2
test/CodeGen/ARM64/fast-isel.ll
View File

@ -87,7 +87,7 @@ entry:
define void @t6() nounwind {
; CHECK: t6
; CHECK: brk #1
; CHECK: brk #0x1
tail call void @llvm.trap()
ret void
}

4
test/CodeGen/ARM64/fcopysign.ll
View File

@ -5,7 +5,7 @@
define float @test1(float %x, float %y) nounwind {
entry:
; CHECK-LABEL: test1:
; CHECK: movi.4s v2, #128, lsl #24
; CHECK: movi.4s v2, #0x80, lsl #24
; CHECK: bit.16b v0, v1, v2
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
ret float %0
@ -37,7 +37,7 @@ define float @test4() nounwind {
entry:
; CHECK-LABEL: test4:
; CHECK: fcvt s0, d0
; CHECK: movi.4s v[[CONST:[0-9]+]], #128, lsl #24
; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24
; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]]
%0 = tail call double (...)* @bar() nounwind
%1 = fptrunc double %0 to float

2
test/CodeGen/ARM64/trap.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm64 | FileCheck %s
define void @foo() nounwind {
; CHECK: foo
; CHECK: brk #1
; CHECK: brk #0x1
tail call void @llvm.trap()
ret void
}

2
test/CodeGen/ARM64/vector-ext.ll
View File

@ -2,7 +2,7 @@
;CHECK: @func30
;CHECK: ushll.4s v0, v0, #0
;CHECK: movi.4s v1, #1
;CHECK: movi.4s v1, #0x1
;CHECK: and.16b v0, v0, v1
;CHECK: str q0, [x0]
;CHECK: ret

18
test/CodeGen/ARM64/vector-imm.ll
View File

@ -50,35 +50,35 @@ define <2 x double> @foo(<2 x double> %bar) nounwind {
define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t1:
; CHECK: movi.4s v0, #75
; CHECK: movi.4s v0, #0x4b
ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
}
define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t2:
; CHECK: movi.4s v0, #75, lsl #8
; CHECK: movi.4s v0, #0x4b, lsl #8
ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
}
define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t3:
; CHECK: movi.4s v0, #75, lsl #16
; CHECK: movi.4s v0, #0x4b, lsl #16
ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
}
define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t4:
; CHECK: movi.4s v0, #75, lsl #24
; CHECK: movi.4s v0, #0x4b, lsl #24
ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
}
define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_8h_imm_t5:
; CHECK: movi.8h v0, #75
; CHECK: movi.8h v0, #0x4b
ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
}
@ -86,28 +86,28 @@ entry:
define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_8h_imm_t6:
; CHECK: movi.8h v0, #75, lsl #8
; CHECK: movi.8h v0, #0x4b, lsl #8
ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
}
define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t7:
; CHECK: movi.4s v0, #75, msl #8
; CHECK: movi.4s v0, #0x4b, msl #8
ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
}
define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t8:
; CHECK: movi.4s v0, #75, msl #16
; CHECK: movi.4s v0, #0x4b, msl #16
ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
}
define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_16b_imm_t9:
; CHECK: movi.16b v0, #75
; CHECK: movi.16b v0, #0x4b
ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
}

2
test/CodeGen/ARM64/vshuffle.ll
View File

@ -15,7 +15,7 @@
; CHECK: .byte 0 ; 0x0
; CHECK: test1
; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
; CHECK: movi.8h v[[REG1:[0-9]+]], #1, lsl #8
; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8
; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
define <8 x i1> @test1() {
entry:

148
test/MC/ARM64/advsimd.s
View File

@ -780,19 +780,19 @@ foo:
bic.2s v0, #1, lsl #16
bic.2s v0, #1, lsl #24
; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f]
; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f]
; CHECK: bic.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f]
; CHECK: bic.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f]
; CHECK: bic.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f]
; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f]
; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f]
; CHECK: bic.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f]
; CHECK: bic.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f]
; CHECK: bic.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f]
bic.4h v0, #1
bic.4h v0, #1, lsl #0
bic.4h v0, #1, lsl #8
; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f]
; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f]
; CHECK: bic.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f]
; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f]
; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f]
; CHECK: bic.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f]
bic.4s v0, #1
bic.4s v0, #1, lsl #0
@ -800,19 +800,19 @@ foo:
bic.4s v0, #1, lsl #16
bic.4s v0, #1, lsl #24
; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f]
; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f]
; CHECK: bic.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f]
; CHECK: bic.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f]
; CHECK: bic.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f]
; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f]
; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f]
; CHECK: bic.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f]
; CHECK: bic.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f]
; CHECK: bic.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f]
bic.8h v0, #1
bic.8h v0, #1, lsl #0
bic.8h v0, #1, lsl #8
; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f]
; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f]
; CHECK: bic.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f]
; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f]
; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f]
; CHECK: bic.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f]
fmov.2d v0, #1.250000e-01
@ -830,19 +830,19 @@ foo:
orr.2s v0, #1, lsl #16
orr.2s v0, #1, lsl #24
; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f]
; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f]
; CHECK: orr.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f]
; CHECK: orr.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f]
; CHECK: orr.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f]
; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f]
; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f]
; CHECK: orr.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f]
; CHECK: orr.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f]
; CHECK: orr.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f]
orr.4h v0, #1
orr.4h v0, #1, lsl #0
orr.4h v0, #1, lsl #8
; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f]
; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f]
; CHECK: orr.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f]
; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f]
; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f]
; CHECK: orr.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f]
orr.4s v0, #1
orr.4s v0, #1, lsl #0
@ -850,19 +850,19 @@ foo:
orr.4s v0, #1, lsl #16
orr.4s v0, #1, lsl #24
; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f]
; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f]
; CHECK: orr.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f]
; CHECK: orr.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f]
; CHECK: orr.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f]
; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f]
; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f]
; CHECK: orr.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f]
; CHECK: orr.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f]
; CHECK: orr.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f]
orr.8h v0, #1
orr.8h v0, #1, lsl #0
orr.8h v0, #1, lsl #8
; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f]
; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f]
; CHECK: orr.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f]
; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f]
; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f]
; CHECK: orr.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f]
movi d0, #0x000000000000ff
movi.2d v0, #0x000000000000ff
@ -876,11 +876,11 @@ foo:
movi.2s v0, #1, lsl #16
movi.2s v0, #1, lsl #24
; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f]
; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f]
; CHECK: movi.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f]
; CHECK: movi.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f]
; CHECK: movi.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f]
; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f]
; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f]
; CHECK: movi.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f]
; CHECK: movi.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f]
; CHECK: movi.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f]
movi.4s v0, #1
movi.4s v0, #1, lsl #0
@ -888,43 +888,43 @@ foo:
movi.4s v0, #1, lsl #16
movi.4s v0, #1, lsl #24
; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f]
; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f]
; CHECK: movi.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f]
; CHECK: movi.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f]
; CHECK: movi.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f]
; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f]
; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f]
; CHECK: movi.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f]
; CHECK: movi.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f]
; CHECK: movi.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f]
movi.4h v0, #1
movi.4h v0, #1, lsl #0
movi.4h v0, #1, lsl #8
; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f]
; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f]
; CHECK: movi.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f]
; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f]
; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f]
; CHECK: movi.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f]
movi.8h v0, #1
movi.8h v0, #1, lsl #0
movi.8h v0, #1, lsl #8
; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f]
; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f]
; CHECK: movi.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f]
; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f]
; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f]
; CHECK: movi.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f]
movi.2s v0, #1, msl #8
movi.2s v0, #1, msl #16
movi.4s v0, #1, msl #8
movi.4s v0, #1, msl #16
; CHECK: movi.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f]
; CHECK: movi.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f]
; CHECK: movi.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f]
; CHECK: movi.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f]
; CHECK: movi.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f]
; CHECK: movi.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f]
; CHECK: movi.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f]
; CHECK: movi.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f]
movi.8b v0, #1
movi.16b v0, #1
; CHECK: movi.8b v0, #1 ; encoding: [0x20,0xe4,0x00,0x0f]
; CHECK: movi.16b v0, #1 ; encoding: [0x20,0xe4,0x00,0x4f]
; CHECK: movi.8b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x0f]
; CHECK: movi.16b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x4f]
mvni.2s v0, #1
mvni.2s v0, #1, lsl #0
@ -932,11 +932,11 @@ foo:
mvni.2s v0, #1, lsl #16
mvni.2s v0, #1, lsl #24
; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f]
; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f]
; CHECK: mvni.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f]
; CHECK: mvni.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f]
; CHECK: mvni.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f]
; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f]
; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f]
; CHECK: mvni.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f]
; CHECK: mvni.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f]
; CHECK: mvni.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f]
mvni.4s v0, #1
mvni.4s v0, #1, lsl #0
@ -944,37 +944,37 @@ foo:
mvni.4s v0, #1, lsl #16
mvni.4s v0, #1, lsl #24
; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f]
; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f]
; CHECK: mvni.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f]
; CHECK: mvni.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f]
; CHECK: mvni.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f]
; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f]
; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f]
; CHECK: mvni.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f]
; CHECK: mvni.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f]
; CHECK: mvni.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f]
mvni.4h v0, #1
mvni.4h v0, #1, lsl #0
mvni.4h v0, #1, lsl #8
; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f]
; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f]
; CHECK: mvni.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f]
; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f]
; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f]
; CHECK: mvni.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f]
mvni.8h v0, #1
mvni.8h v0, #1, lsl #0
mvni.8h v0, #1, lsl #8
; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f]
; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f]
; CHECK: mvni.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f]
; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f]
; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f]
; CHECK: mvni.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f]
mvni.2s v0, #1, msl #8
mvni.2s v0, #1, msl #16
mvni.4s v0, #1, msl #8
mvni.4s v0, #1, msl #16
; CHECK: mvni.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f]
; CHECK: mvni.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f]
; CHECK: mvni.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f]
; CHECK: mvni.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f]
; CHECK: mvni.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f]
; CHECK: mvni.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f]
; CHECK: mvni.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f]
; CHECK: mvni.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f]
;===-------------------------------------------------------------------------===
; AdvSIMD scalar x index

6
test/MC/ARM64/aliases.s
View File

@ -746,8 +746,8 @@ foo:
movi v2.2D, #0x000000000000ff
; CHECK: movi.16b v4, #0 ; encoding: [0x04,0xe4,0x00,0x4f]
; CHECK: movi.16b v4, #1 ; encoding: [0x24,0xe4,0x00,0x4f]
; CHECK: movi.8b v4, #2 ; encoding: [0x44,0xe4,0x00,0x0f]
; CHECK: movi.8b v4, #3 ; encoding: [0x64,0xe4,0x00,0x0f]
; CHECK: movi.16b v4, #0x1 ; encoding: [0x24,0xe4,0x00,0x4f]
; CHECK: movi.8b v4, #0x2 ; encoding: [0x44,0xe4,0x00,0x0f]
; CHECK: movi.8b v4, #0x3 ; encoding: [0x64,0xe4,0x00,0x0f]
; CHECK: movi.2d v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f]
; CHECK: movi.2d v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f]

111
test/MC/Disassembler/ARM64/advsimd.txt
View File

@ -535,18 +535,18 @@
0x20 0x54 0x00 0x2f
0x20 0x74 0x00 0x2f
# CHECK: bic.2s v0, #1
# CHECK: bic.2s v0, #1, lsl #8
# CHECK: bic.2s v0, #1, lsl #16
# CHECK: bic.2s v0, #1, lsl #24
# CHECK: bic.2s v0, #0x1
# CHECK: bic.2s v0, #0x1, lsl #8
# CHECK: bic.2s v0, #0x1, lsl #16
# CHECK: bic.2s v0, #0x1, lsl #24
0x20 0x94 0x00 0x2f
0x20 0x94 0x00 0x2f
0x20 0xb4 0x00 0x2f
# CHECK: bic.4h v0, #1
# CHECK: bic.4h v0, #1
# FIXME: bic.4h v0, #1, lsl #8
# CHECK: bic.4h v0, #0x1
# CHECK: bic.4h v0, #0x1
# FIXME: bic.4h v0, #0x1, lsl #8
# 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
0x20 0x14 0x00 0x6f
@ -554,16 +554,16 @@
0x20 0x54 0x00 0x6f
0x20 0x74 0x00 0x6f
# CHECK: bic.4s v0, #1
# CHECK: bic.4s v0, #1, lsl #8
# CHECK: bic.4s v0, #1, lsl #16
# CHECK: bic.4s v0, #1, lsl #24
# CHECK: bic.4s v0, #0x1
# CHECK: bic.4s v0, #0x1, lsl #8
# CHECK: bic.4s v0, #0x1, lsl #16
# CHECK: bic.4s v0, #0x1, lsl #24
0x20 0x94 0x00 0x6f
0x20 0xb4 0x00 0x6f
# CHECK: bic.8h v0, #1
# FIXME: bic.8h v0, #1, lsl #8
# CHECK: bic.8h v0, #0x1
# FIXME: bic.8h v0, #0x1, lsl #8
# "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
0x00 0xf4 0x02 0x6f
@ -581,16 +581,16 @@
0x20 0x54 0x00 0x0f
0x20 0x74 0x00 0x0f
# CHECK: orr.2s v0, #1
# CHECK: orr.2s v0, #1, lsl #8
# CHECK: orr.2s v0, #1, lsl #16
# CHECK: orr.2s v0, #1, lsl #24
# CHECK: orr.2s v0, #0x1
# CHECK: orr.2s v0, #0x1, lsl #8
# CHECK: orr.2s v0, #0x1, lsl #16
# CHECK: orr.2s v0, #0x1, lsl #24
0x20 0x94 0x00 0x0f
0x20 0xb4 0x00 0x0f
# CHECK: orr.4h v0, #1
# FIXME: orr.4h v0, #1, lsl #8
# CHECK: orr.4h v0, #0x1
# FIXME: orr.4h v0, #0x1, lsl #8
# 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
0x20 0x14 0x00 0x4f
@ -598,17 +598,16 @@
0x20 0x54 0x00 0x4f
0x20 0x74 0x00 0x4f
# CHECK: orr.4s v0, #1
# CHECK: orr.4s v0, #1, lsl #8
# CHECK: orr.4s v0, #1, lsl #16
# CHECK: orr.4s v0, #1, lsl #24
# CHECK: orr.4s v0, #0x1
# CHECK: orr.4s v0, #0x1, lsl #8
# CHECK: orr.4s v0, #0x1, lsl #16
# CHECK: orr.4s v0, #0x1, lsl #24
0x20 0x94 0x00 0x4f
0x20 0xb4 0x00 0x4f
# CHECK: orr.8h v0, #1
# FIXME: orr.8h v0, #1, lsl #8
# "orr.8h" should be selected over "fcvtns.4s v0, v1, #0"
# CHECK: orr.8h v0, #0x1
# CHECK: orr.8h v0, #0x1, lsl #8
0x21 0x70 0x40 0x0c
0x42 0xa0 0x40 0x4c
@ -1445,82 +1444,82 @@
# CHECK: movi d0, #0x000000000000ff
# CHECK: movi.2d v0, #0x000000000000ff
# CHECK: movi.8b v0, #1
# CHECK: movi.16b v0, #1
# CHECK: movi.8b v0, #0x1
# CHECK: movi.16b v0, #0x1
0x20 0x04 0x00 0x0f
0x20 0x24 0x00 0x0f
0x20 0x44 0x00 0x0f
0x20 0x64 0x00 0x0f
# CHECK: movi.2s v0, #1
# CHECK: movi.2s v0, #1, lsl #8
# CHECK: movi.2s v0, #1, lsl #16
# CHECK: movi.2s v0, #1, lsl #24
# CHECK: movi.2s v0, #0x1
# CHECK: movi.2s v0, #0x1, lsl #8
# CHECK: movi.2s v0, #0x1, lsl #16
# CHECK: movi.2s v0, #0x1, lsl #24
0x20 0x04 0x00 0x4f
0x20 0x24 0x00 0x4f
0x20 0x44 0x00 0x4f
0x20 0x64 0x00 0x4f
# CHECK: movi.4s v0, #1
# CHECK: movi.4s v0, #1, lsl #8
# CHECK: movi.4s v0, #1, lsl #16
# CHECK: movi.4s v0, #1, lsl #24
# CHECK: movi.4s v0, #0x1
# CHECK: movi.4s v0, #0x1, lsl #8
# CHECK: movi.4s v0, #0x1, lsl #16
# CHECK: movi.4s v0, #0x1, lsl #24
0x20 0x84 0x00 0x0f
0x20 0xa4 0x00 0x0f
# CHECK: movi.4h v0, #1
# CHECK: movi.4h v0, #1, lsl #8
# CHECK: movi.4h v0, #0x1
# CHECK: movi.4h v0, #0x1, lsl #8
0x20 0x84 0x00 0x4f
0x20 0xa4 0x00 0x4f
# CHECK: movi.8h v0, #1
# CHECK: movi.8h v0, #1, lsl #8
# CHECK: movi.8h v0, #0x1
# CHECK: movi.8h v0, #0x1, lsl #8
0x20 0x04 0x00 0x2f
0x20 0x24 0x00 0x2f
0x20 0x44 0x00 0x2f
0x20 0x64 0x00 0x2f
# CHECK: mvni.2s v0, #1
# CHECK: mvni.2s v0, #1, lsl #8
# CHECK: mvni.2s v0, #1, lsl #16
# CHECK: mvni.2s v0, #1, lsl #24
# CHECK: mvni.2s v0, #0x1
# CHECK: mvni.2s v0, #0x1, lsl #8
# CHECK: mvni.2s v0, #0x1, lsl #16
# CHECK: mvni.2s v0, #0x1, lsl #24
0x20 0x04 0x00 0x6f
0x20 0x24 0x00 0x6f
0x20 0x44 0x00 0x6f
0x20 0x64 0x00 0x6f
# CHECK: mvni.4s v0, #1
# CHECK: mvni.4s v0, #1, lsl #8
# CHECK: mvni.4s v0, #1, lsl #16
# CHECK: mvni.4s v0, #1, lsl #24
# CHECK: mvni.4s v0, #0x1
# CHECK: mvni.4s v0, #0x1, lsl #8
# CHECK: mvni.4s v0, #0x1, lsl #16
# CHECK: mvni.4s v0, #0x1, lsl #24
0x20 0x84 0x00 0x2f
0x20 0xa4 0x00 0x2f
# CHECK: mvni.4h v0, #1
# CHECK: mvni.4h v0, #1, lsl #8
# CHECK: mvni.4h v0, #0x1
# CHECK: mvni.4h v0, #0x1, lsl #8
0x20 0x84 0x00 0x6f
0x20 0xa4 0x00 0x6f
# CHECK: mvni.8h v0, #1
# CHECK: mvni.8h v0, #1, lsl #8
# CHECK: mvni.8h v0, #0x1
# CHECK: mvni.8h v0, #0x1, lsl #8
0x20 0xc4 0x00 0x2f
0x20 0xd4 0x00 0x2f
0x20 0xc4 0x00 0x6f
0x20 0xd4 0x00 0x6f
# CHECK: mvni.2s v0, #1, msl #8
# CHECK: mvni.2s v0, #1, msl #16
# CHECK: mvni.4s v0, #1, msl #8
# CHECK: mvni.4s v0, #1, msl #16
# CHECK: mvni.2s v0, #0x1, msl #8
# CHECK: mvni.2s v0, #0x1, msl #16
# CHECK: mvni.4s v0, #0x1, msl #8
# CHECK: mvni.4s v0, #0x1, msl #16
0x00 0x88 0x21 0x2e
0x00 0x98 0x21 0x2e

16
test/MC/Disassembler/ARM64/branch.txt
View File

@ -24,21 +24,21 @@
#-----------------------------------------------------------------------------
0x20 0x00 0x20 0xd4
# CHECK: brk #1
# CHECK: brk #0x1
0x41 0x00 0xa0 0xd4
# CHECK: dcps1 #2
# CHECK: dcps1 #0x2
0x62 0x00 0xa0 0xd4
# CHECK: dcps2 #3
# CHECK: dcps2 #0x3
0x83 0x00 0xa0 0xd4
# CHECK: dcps3 #4
# CHECK: dcps3 #0x4
0xa0 0x00 0x40 0xd4
# CHECK: hlt #5
# CHECK: hlt #0x5
0xc2 0x00 0x00 0xd4
# CHECK: hvc #6
# CHECK: hvc #0x6
0xe3 0x00 0x00 0xd4
# CHECK: smc #7
# CHECK: smc #0x7
0x01 0x01 0x00 0xd4
# CHECK: svc #8
# CHECK: svc #0x8
#-----------------------------------------------------------------------------
# PC-relative branches (both positive and negative displacement)