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ARM64: scalarize v1i64 mul operation

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This is the second part of fixing PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-09 07:07:02 +00:00
parent 7db3c63bb2
commit 87a79507fa
2 changed files with 9 additions and 0 deletions
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2
lib/Target/ARM64/ARM64ISelLowering.cpp
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@ -173,6 +173,8 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
setOperationAction(ISD::MUL, MVT::v1i64, Expand);
// Custom lowering hooks are needed for XOR
// to fold it into CSINC/CSINV.
setOperationAction(ISD::XOR, MVT::i32, Custom);

7
test/CodeGen/ARM64/vmul.ll
View File

@ -2027,3 +2027,10 @@ define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind {
}
declare <16 x i8> @llvm.arm64.neon.pmull64(i64, i64)
define <1 x i64> @test_mul_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) nounwind {
; CHECK-LABEL: test_mul_v1i64:
; CHECK: mul
%prod = mul <1 x i64> %lhs, %rhs
ret <1 x i64> %prod
}