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Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272476 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
1385fc37d8
commit
87cd6e6baa
@ -31,9 +31,9 @@ class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
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RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
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// The mask VT.
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ValueType KVT = !cast<ValueType>(!if (!eq (NumElts, 1), "i1",
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"v" # NumElts # "i1"));
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ValueType KVT = !cast<ValueType>(!if (!eq (NumElts, 1), "i1",
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"v" # NumElts # "i1"));
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// The GPR register class that can hold the write mask. Use GR8 for fewer
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// than 8 elements. Use shift-right and equal to work around the lack of
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// !lt in tablegen.
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@ -795,31 +795,31 @@ def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs),
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// broadcast with a scalar argument.
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multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
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let isCodeGenOnly = 1 in {
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def r_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
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(ins SrcInfo.FRC:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}",
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[(set DestInfo.RC:$dst, (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)))]>,
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Requires<[HasAVX512]>, T8PD, EVEX;
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let Constraints = "$src0 = $dst" in
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def rk_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
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(ins DestInfo.RC:$src0, DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
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OpcodeStr#"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
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[(set DestInfo.RC:$dst,
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[(set DestInfo.RC:$dst,
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(vselect DestInfo.KRCWM:$mask,
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(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
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DestInfo.RC:$src0))]>,
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Requires<[HasAVX512]>, T8PD, EVEX, EVEX_K;
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Requires<[HasAVX512]>, T8PD, EVEX, EVEX_K;
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def rkz_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
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(ins DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
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OpcodeStr#"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
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[(set DestInfo.RC:$dst,
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[(set DestInfo.RC:$dst,
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(vselect DestInfo.KRCWM:$mask,
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(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
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DestInfo.ImmAllZerosV))]>,
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Requires<[HasAVX512]>, T8PD, EVEX, EVEX_KZ;
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Requires<[HasAVX512]>, T8PD, EVEX, EVEX_KZ;
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} // let isCodeGenOnly = 1 in
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}
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@ -839,9 +839,9 @@ multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
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let isCodeGenOnly = 1 in
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defm m_Int : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
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(ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
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(DestInfo.VT
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(X86VBroadcast
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(SrcInfo.VT (scalar_to_vector
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(DestInfo.VT
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(X86VBroadcast
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(SrcInfo.VT (scalar_to_vector
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(SrcInfo.ScalarLdFrag addr:$src)))))>,
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T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
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}
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@ -863,9 +863,9 @@ let ExeDomain = SSEPackedSingle in {
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defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
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avx512vl_f32_info>;
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let Predicates = [HasVLX] in {
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defm VBROADCASTSSZ128 :
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avx512_broadcast_rm<0x18, "vbroadcastss", v4f32x_info, v4f32x_info>,
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avx512_broadcast_scalar<0x18, "vbroadcastss", v4f32x_info, v4f32x_info>,
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defm VBROADCASTSSZ128 :
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avx512_broadcast_rm<0x18, "vbroadcastss", v4f32x_info, v4f32x_info>,
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avx512_broadcast_scalar<0x18, "vbroadcastss", v4f32x_info, v4f32x_info>,
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EVEX_V128;
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}
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}
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@ -883,8 +883,8 @@ def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
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multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
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RegisterClass SrcRC> {
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defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins SrcRC:$src),
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"vpbroadcast"##_.Suffix, "$src", "$src",
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(ins SrcRC:$src),
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"vpbroadcast"##_.Suffix, "$src", "$src",
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(_.VT (X86VBroadcast SrcRC:$src))>, T8PD, EVEX;
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}
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@ -908,7 +908,7 @@ let isAsmParserOnly = 1 in {
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defm VPBROADCASTBr_Alt : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info,
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GR32, HasBWI>;
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defm VPBROADCASTWr_Alt : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info,
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GR32, HasBWI>;
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GR32, HasBWI>;
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}
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defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
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HasAVX512>;
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@ -958,10 +958,10 @@ defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
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multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
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defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
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defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
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(ins _Src.MemOp:$src), OpcodeStr, "$src", "$src",
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(_Dst.VT (X86SubVBroadcast
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(_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
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(_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
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AVX5128IBase, EVEX;
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}
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@ -1053,7 +1053,7 @@ multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
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[(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
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}
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multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
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multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
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let Predicates = [HasCDI] in
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defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
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@ -1830,7 +1830,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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let AddedComplexity = 20 in {
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@ -1845,7 +1845,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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}
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@ -1866,21 +1866,21 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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[(set _.KRC:$dst,(or _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##mem#
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set _.KRC:$dst,(OpNode
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[(set _.KRC:$dst,(OpNode
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(_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2)))], NoItinerary>;
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def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
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OpcodeStr##_.Suffix##mem#
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
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[(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
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[(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
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(_.VT (bitconvert (_.LdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>, EVEX_K;
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def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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@ -1888,8 +1888,8 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
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_.BroadcastStr##", $dst|$dst, ${src1}"
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##_.BroadcastStr##", $src2}",
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[(set _.KRC:$dst,(OpNode
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(_.VT (X86VBroadcast
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[(set _.KRC:$dst,(OpNode
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2)))], NoItinerary>,EVEX_B;
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def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
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@ -1897,18 +1897,18 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
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_.BroadcastStr##", $dst {${mask}}|$dst {${mask}}, ${src1}"##
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_.BroadcastStr##", $src2}",
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[(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
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(_.VT (X86VBroadcast
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[(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src1))),
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(i32 imm:$src2))))], NoItinerary>,
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EVEX_B, EVEX_K;
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}
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multiclass avx512_vector_fpclass_all<string OpcodeStr,
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
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AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
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string broadcast>{
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let Predicates = [prd] in {
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defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
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defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
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broadcast>, EVEX_V512;
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}
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let Predicates = [prd, HasVLX] in {
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@ -2421,9 +2421,9 @@ multiclass operation_subvector_mask_lowering<RegisterClass subRC, ValueType subV
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RegisterClass RC, ValueType VT> {
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def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
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(subVT (COPY_TO_REGCLASS RC:$src, subRC))>;
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def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
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(VT (COPY_TO_REGCLASS subRC:$src, RC))>;
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(VT (COPY_TO_REGCLASS subRC:$src, RC))>;
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}
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defm : operation_subvector_mask_lowering<VK2, v2i1, VK4, v4i1>;
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@ -2447,11 +2447,11 @@ defm : operation_subvector_mask_lowering<VK16, v16i1, VK64, v64i1>;
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defm : operation_subvector_mask_lowering<VK32, v32i1, VK64, v64i1>;
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def : Pat<(v2i1 (extract_subvector (v4i1 VK4:$src), (iPTR 2))),
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(v2i1 (COPY_TO_REGCLASS
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(v2i1 (COPY_TO_REGCLASS
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(KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16), (i8 2)),
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VK2))>;
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def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 4))),
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(v4i1 (COPY_TO_REGCLASS
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(v4i1 (COPY_TO_REGCLASS
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(KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (i8 4)),
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VK4))>;
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def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
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@ -3920,7 +3920,7 @@ multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
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defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1,
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(OpNode _.RC:$src1,
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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(i32 FROUND_CURRENT))>;
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}
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@ -5033,31 +5033,31 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT ,
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EVEX, VEX_LIG;
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def rb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc),
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!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
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[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))]>,
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[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))]>,
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EVEX, VEX_LIG, EVEX_B, EVEX_RC;
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def rm : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.ScalarMemOp:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstVT.RC:$dst, (OpNode
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[(set DstVT.RC:$dst, (OpNode
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(SrcVT.VT (scalar_to_vector (SrcVT.ScalarLdFrag addr:$src))),
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(i32 FROUND_CURRENT)))]>,
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(i32 FROUND_CURRENT)))]>,
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EVEX, VEX_LIG;
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} // Predicates = [HasAVX512]
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} // Predicates = [HasAVX512]
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}
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// Convert float/double to signed/unsigned int 32/64
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defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
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defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
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X86cvts2si, "cvtss2si">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
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defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
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X86cvts2si, "cvtss2si">,
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XS, VEX_W, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
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defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
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X86cvts2usi, "cvtss2usi">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
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defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
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X86cvts2usi, "cvtss2usi">, XS, VEX_W,
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EVEX_CD8<32, CD8VT1>;
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defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
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defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
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X86cvts2si, "cvtsd2si">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
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@ -6124,8 +6124,8 @@ avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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(i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
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defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
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OpcodeStr,
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(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
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OpcodeStr,
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"$src3, $src2, $src1", "$src1, $src2, $src3",
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(_.VT (X86RndScales (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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@ -6426,11 +6426,11 @@ multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
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multiclass avx512_extend_lowering<SDPatternOperator OpNode, X86VectorVTInfo To,
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X86VectorVTInfo From, SubRegIndex SubRegIdx> {
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def : Pat<(To.VT (OpNode (From.VT From.RC:$src))),
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(!cast<Instruction>(NAME#To.ZSuffix#"rr")
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(!cast<Instruction>(NAME#To.ZSuffix#"rr")
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(EXTRACT_SUBREG From.RC:$src, SubRegIdx))>;
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}
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multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr,
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multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode, bit IsCodeGenOnly,
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string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
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let Predicates = [HasVLX, HasBWI] in {
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@ -6450,7 +6450,7 @@ multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr,
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr,
|
||||
multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr,
|
||||
SDPatternOperator OpNode, bit IsCodeGenOnly,
|
||||
string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
|
||||
let Predicates = [HasVLX, HasAVX512] in {
|
||||
@ -6470,7 +6470,7 @@ multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr,
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr,
|
||||
multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr,
|
||||
SDPatternOperator OpNode, bit IsCodeGenOnly,
|
||||
string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
|
||||
let Predicates = [HasVLX, HasAVX512] in {
|
||||
@ -6490,7 +6490,7 @@ multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr,
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr,
|
||||
multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr,
|
||||
SDPatternOperator OpNode, bit IsCodeGenOnly,
|
||||
string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
|
||||
let Predicates = [HasVLX, HasAVX512] in {
|
||||
@ -6510,7 +6510,7 @@ multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr,
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr,
|
||||
multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr,
|
||||
SDPatternOperator OpNode, bit IsCodeGenOnly,
|
||||
string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
|
||||
let Predicates = [HasVLX, HasAVX512] in {
|
||||
@ -6530,7 +6530,7 @@ multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr,
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr,
|
||||
multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr,
|
||||
SDPatternOperator OpNode, bit IsCodeGenOnly,
|
||||
string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user