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Fix edge condition in DAGCombiner to improve codegen of shift sequences.
When canonicalizing dags according to the rule (shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1)) remember to add the new shl dag to the DAGCombiner worklist of nodes. If we don't explicitly add it to the worklist of nodes to visit, we may not trigger later on the rule that folds the shift left + logical shift right into a AND instruction with bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192883 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3794,6 +3794,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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EVT CountVT = NewOp0.getOperand(1).getValueType();
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EVT CountVT = NewOp0.getOperand(1).getValueType();
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SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
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SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
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NewOp0, DAG.getConstant(c2, CountVT));
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NewOp0, DAG.getConstant(c2, CountVT));
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AddToWorkList(NewSHL.getNode());
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
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}
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}
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}
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}
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@ -187,6 +187,8 @@ entry:
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; Once the add is removed, the number of uses becomes one and therefore the
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; Once the add is removed, the number of uses becomes one and therefore the
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; dags are canonicalized. After Legalization, we need to make sure that the
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; dags are canonicalized. After Legalization, we need to make sure that the
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; valuetype for the shift count is legal.
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; valuetype for the shift count is legal.
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; Verify also that we correctly fold the shl-shr sequence into an
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; AND with bitmask.
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define void @g(i32 %a) {
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define void @g(i32 %a) {
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%b = lshr i32 %a, 2
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%b = lshr i32 %a, 2
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@ -197,5 +199,11 @@ define void @g(i32 %a) {
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ret void
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ret void
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}
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}
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; CHECK-LABEL: @g
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: and
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; CHECK-NEXT: jmp
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declare void @f(i64)
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declare void @f(i64)
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