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avoid using a constant table when a constant can be used inline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32580 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -660,14 +660,91 @@ static SDOperand GetARMCC(ISD::CondCode CC, MVT::ValueType vt,
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return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32);
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}
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static bool isUInt8Immediate(uint32_t x) {
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return x < (1 << 8);
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}
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static uint32_t rotateL(uint32_t x) {
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uint32_t bit31 = (x & (1 << 31)) >> 31;
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uint32_t t = x << 1;
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return t | bit31;
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}
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static bool isRotInt8Immediate(uint32_t x) {
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int r;
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for (r = 0; r < 16; r++) {
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if (isUInt8Immediate(x))
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return true;
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x = rotateL(rotateL(x));
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}
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return false;
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}
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static void LowerCMP(SDOperand &Cmp, SDOperand &ARMCC, SDOperand LHS,
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SDOperand RHS, ISD::CondCode CC, SelectionDAG &DAG) {
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MVT::ValueType vt = LHS.getValueType();
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if (vt == MVT::i32) {
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assert(!isa<ConstantSDNode>(LHS));
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if (ConstantSDNode *SD_C = dyn_cast<ConstantSDNode>(RHS.Val)) {
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uint32_t C = SD_C->getValue();
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uint32_t NC;
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switch(CC) {
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default:
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NC = C; break;
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case ISD::SETLT:
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case ISD::SETULT:
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case ISD::SETGE:
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case ISD::SETUGE:
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NC = C - 1; break;
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case ISD::SETLE:
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case ISD::SETULE:
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case ISD::SETGT:
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case ISD::SETUGT:
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NC = C + 1; break;
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}
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ISD::CondCode NCC;
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switch(CC) {
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default:
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NCC = CC; break;
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case ISD::SETLT:
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NCC = ISD::SETLE; break;
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case ISD::SETULT:
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NCC = ISD::SETULE; break;
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case ISD::SETGE:
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NCC = ISD::SETGT; break;
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case ISD::SETUGE:
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NCC = ISD::SETUGT; break;
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case ISD::SETLE:
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NCC = ISD::SETLT; break;
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case ISD::SETULE:
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NCC = ISD::SETULT; break;
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case ISD::SETGT:
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NCC = ISD::SETGE; break;
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case ISD::SETUGT:
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NCC = ISD::SETUGE; break;
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}
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if (!isRotInt8Immediate(C) && isRotInt8Immediate(NC)) {
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RHS = DAG.getConstant(NC, MVT::i32);
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CC = NCC;
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}
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}
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}
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Cmp = GetCMP(CC, LHS, RHS, DAG);
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ARMCC = GetARMCC(CC, vt, DAG);
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}
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static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG);
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SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
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SDOperand Cmp;
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SDOperand ARMCC;
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LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
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return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
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}
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@ -677,8 +754,9 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand LHS = Op.getOperand(2);
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG);
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SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
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SDOperand Cmp;
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SDOperand ARMCC;
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LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
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return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
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}
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@ -820,26 +898,6 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
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return isInt12Immediate(Op.Val, Imm);
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}
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static uint32_t rotateL(uint32_t x) {
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uint32_t bit31 = (x & (1 << 31)) >> 31;
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uint32_t t = x << 1;
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return t | bit31;
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}
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static bool isUInt8Immediate(uint32_t x) {
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return x < (1 << 8);
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}
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static bool isRotInt8Immediate(uint32_t x) {
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int r;
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for (r = 0; r < 16; r++) {
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if (isUInt8Immediate(x))
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return true;
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x = rotateL(rotateL(x));
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}
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return false;
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}
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bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand Op,
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SDOperand N,
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SDOperand &Arg,
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@ -5,6 +5,7 @@
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; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep ".word.*257" | wc -l | grep 1 &&
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; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "mov r0, #-1073741761" | wc -l | grep 1 &&
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; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "mov r0, #1008" | wc -l | grep 1 &&
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; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "cmp r0, #65536" | wc -l | grep 1 &&
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; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "\.comm.*a,4,4" | wc -l | grep 1
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%a = internal global int 0
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@ -32,3 +33,12 @@ uint %f5() {
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uint %f6() {
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ret uint 1008
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}
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void %f7(uint %a) {
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entry:
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%b = setgt uint %a, 65536
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br bool %b, label %r, label %r
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r:
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ret void
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}
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