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Give RegAllocSimple a TargetInstrInfo member to keep it consistent

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with RegAllocLocal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-07-09 19:56:01 +00:00
parent 8849054624
commit 88cef2480f
1 changed files with 2 additions and 2 deletions
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4
lib/CodeGen/RegAllocSimple.cpp
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@ -46,6 +46,7 @@ namespace {
MachineFunction *MF; MachineFunction *MF;
const TargetMachine *TM; const TargetMachine *TM;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled // these values are spilled
@ -144,7 +145,6 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s) // Add move instruction(s)
++NumLoads; ++NumLoads;
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg; return PhysReg;
} }
@ -153,7 +153,6 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) { unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
int FrameIdx = getStackSpaceFor(VirtReg, RC); int FrameIdx = getStackSpaceFor(VirtReg, RC);
@ -240,6 +239,7 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
MF = &Fn; MF = &Fn;
TM = &MF->getTarget(); TM = &MF->getTarget();
TRI = TM->getRegisterInfo(); TRI = TM->getRegisterInfo();
TII = TM->getInstrInfo();
// Loop over all of the basic blocks, eliminating virtual register references // Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();