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ARM VFP assembly parsing for VADD and VSUB two-operand forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1178,6 +1178,16 @@ def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
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(VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
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def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
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(VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
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// VADD has a two-operand form (implied destination operand)
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def : VFP2InstAlias<"vadd${p}.f64 $Dn, $Dm",
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(VADDD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
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def : VFP2InstAlias<"vadd${p}.f32 $Sn, $Sm",
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(VADDS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
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// VSUB has a two-operand form (implied destination operand)
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def : VFP2InstAlias<"vsub${p}.f64 $Dn, $Dm",
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(VSUBD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
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def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm",
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(VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
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// VMOV can accept optional .f32/.f64 suffix.
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def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn",
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