FrameIndex could be used as a value (addressof (arg)) or as an address.

Expand it exactly like GlobalAddress.
Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72776 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PIC16/PIC16ISelLowering.cpp

@@ -359,11 +359,23 @@ SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
   // Expand FrameIndex like GlobalAddress and ExternalSymbol
   // Also use Offset field for lo and hi parts. The default 
   // offset is zero.
+
+  /*
   SDValue Offset = DAG.getConstant(0, MVT::i8);
   SDValue FI = DAG.getTargetFrameIndex(Index, MVT::i8);
   SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, FI, Offset);
   SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, FI, Offset);
   return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
+  */
+
+  SDValue ES;
+  int FrameOffset;
+  SDValue FI = SDValue(N,0);
+  LegalizeFrameIndex(FI, DAG, ES, FrameOffset);
+  SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8);
+  SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset);
+  SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset);
+  return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi);
 }
 
 
@@ -626,12 +638,22 @@ void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
   // Expansion of FrameIndex has Lo/Hi parts
   if (isDirectAddress(Ptr)) { 
       SDValue TFI = Ptr.getOperand(0).getOperand(0); 
+      int FrameOffset;
       if (TFI.getOpcode() == ISD::TargetFrameIndex) {
-        int FrameOffset;
         LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset);
         Hi = DAG.getConstant(1, MVT::i8);
         Offset += FrameOffset; 
         return;
+      } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) {
+        // FrameIndex has already been expanded.
+        // Now just make use of its expansion
+        Lo = TFI;
+        Hi = DAG.getConstant(1, MVT::i8);
+        SDValue FOffset = Ptr.getOperand(0).getOperand(1);
+        assert (FOffset.getOpcode() == ISD::Constant && 
+                          "Invalid operand of PIC16ISD::Lo");
+        Offset += dyn_cast<ConstantSDNode>(FOffset)->getZExtValue();
+        return;
       }
   }
 
@@ -721,7 +743,8 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
       for (iter=MemBytes; iter<ExtdBytes; ++iter) { 
         PICLoads.push_back(SRA);
       }
-    } else if (ISD::isZEXTLoad(N)) {
+    } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) {
+    //} else if (ISD::isZEXTLoad(N)) {
       // ZeroExtendedLoad -- For all ExtdBytes use constant 0
       SDValue ConstZero = DAG.getConstant(0, MVT::i8);
       for (iter=MemBytes; iter<ExtdBytes; ++iter) { 

lib/Target/PIC16/PIC16InstrInfo.cpp

@@ -184,3 +184,31 @@ bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
   return false;
 }
 
+/// InsertBranch - Insert a branch into the end of the specified
+/// MachineBasicBlock.  This operands to this method are the same as those
+/// returned by AnalyzeBranch.  This is invoked in cases where AnalyzeBranch
+/// returns success and when an unconditional branch (TBB is non-null, FBB is
+/// null, Cond is empty) needs to be inserted. It returns the number of
+/// instructions inserted.
+unsigned PIC16InstrInfo::
+InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 
+             MachineBasicBlock *FBB,
+             const SmallVectorImpl<MachineOperand> &Cond) const {
+  // Shouldn't be a fall through.
+  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
+
+  if (FBB == 0) { // One way branch.
+    if (Cond.empty()) {
+      // Unconditional branch?
+      DebugLoc dl = DebugLoc::getUnknownLoc();
+      BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
+    }
+    return 1;
+  }
+
+  // FIXME: If the there are some conditions specified then conditional branch
+  // should be generated.   
+  // For the time being no instruction is being generated therefore
+  // returning NULL.
+  return 0;
+}

lib/Target/PIC16/PIC16InstrInfo.h

@@ -64,6 +64,11 @@ public:
                            unsigned &SrcReg, unsigned &DstReg,
                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
 
+  virtual 
+  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                        MachineBasicBlock *FBB,
+                        const SmallVectorImpl<MachineOperand> &Cond) const; 
+
   };
 } // namespace llvm
 

lib/Target/PIC16/PIC16InstrInfo.td

@@ -189,22 +189,22 @@ def movlw : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
 
 // Move a Lo(TGA) to W.
 def movlw_lo_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw LOW(${src}) + ${src2}",
+                      "movlw LOW(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Lo tglobaladdr:$src, imm:$src2 ))]>;
 
 // Move a Lo(TES) to W.
 def movlw_lo_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw LOW(${src}) + ${src2}",
+                      "movlw LOW(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Lo texternalsym:$src, imm:$src2 ))]>;
 
 // Move a Hi(TGA) to W.
 def movlw_hi_1 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw HIGH(${src}) + ${src2}",
+                      "movlw HIGH(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Hi tglobaladdr:$src, imm:$src2))]>;
 
 // Move a Hi(TES) to W.
 def movlw_hi_2 : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src, i8imm:$src2),
-                      "movlw HIGH(${src}) + ${src2}",
+                      "movlw HIGH(${src} + ${src2})",
                       [(set GPR:$dst, (PIC16Hi texternalsym:$src, imm:$src2))]>;
 }