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Don't prevent a vselect of constants from becoming a single load (PR20648).
Fix for PR20648 - http://llvm.org/bugs/show_bug.cgi?id=20648 This patch checks the operands of a vselect to see if all values are constants. If yes, bail out of any further attempts to create a blend or shuffle because SelectionDAGLegalize knows how to turn this kind of vselect into a single load. This already happens for machines without SSE4.1, so the added checks just send more targets down that path. Differential Revision: http://reviews.llvm.org/D4934 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216121 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -10416,6 +10416,13 @@ static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
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}
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SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
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// A vselect where all conditions and data are constants can be optimized into
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// a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
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if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
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ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
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ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
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return SDValue();
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SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
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if (BlendOp.getNode())
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return BlendOp;
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@ -20419,6 +20426,12 @@ TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
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if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
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return SDValue();
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// A vselect where all conditions and data are constants can be optimized into
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// a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
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if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
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ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
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return SDValue();
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unsigned MaskValue = 0;
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if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
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return SDValue();
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@ -138,3 +138,13 @@ define <8 x i16> @blend_shufflevector_8xi16(<8 x i16> %a, <8 x i16> %b) {
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%1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 15>
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ret <8 x i16> %1
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}
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; PR20648 - a blend of constants isn't really a blend; it's just a constant pool load.
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; CHECK-LABEL: @does_not_blend
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; CHECK: movaps
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; CHECK-NEXT: ret
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define <4 x i32> @does_not_blend() {
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%select = select <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %select
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}
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