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[GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES.
Summary: [GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES. Reviewers: zvi, t.p.northover, guyblank Reviewed By: t.p.northover Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32288 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Igor Breger
parent
e5d13111d7
commit
8978f2978f
@ -53,7 +53,6 @@ void X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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return;
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}
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SmallVector<uint64_t, 4> BitOffsets;
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SmallVector<unsigned, 8> SplitRegs;
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EVT PartVT = TLI.getRegisterType(Context, VT);
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@ -64,8 +63,10 @@ void X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
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PartTy, OrigArg.Flags};
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SplitArgs.push_back(Info);
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PerformArgSplit(Info.Reg, PartVT.getSizeInBits() * i);
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SplitRegs.push_back(Info.Reg);
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}
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PerformArgSplit(SplitRegs);
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}
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namespace {
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@ -112,10 +113,9 @@ bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
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SmallVector<ArgInfo, 8> SplitArgs;
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splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
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[&](unsigned Reg, uint64_t Offset) {
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MIRBuilder.buildExtract(Reg, VReg, Offset);
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});
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splitToValueTypes(
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OrigArg, SplitArgs, DL, MRI,
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[&](ArrayRef<unsigned> Regs) { MIRBuilder.buildUnmerge(Regs, VReg); });
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FuncReturnHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
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if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
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@ -183,22 +183,10 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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for (auto &Arg : F.args()) {
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ArgInfo OrigArg(VRegs[Idx], Arg.getType());
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setArgFlags(OrigArg, Idx + 1, DL, F);
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LLT Ty = MRI.getType(VRegs[Idx]);
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unsigned Dst = VRegs[Idx];
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bool Split = false;
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splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
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[&](unsigned Reg, uint64_t Offset) {
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if (!Split) {
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Split = true;
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Dst = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildUndef(Dst);
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}
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unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset);
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Dst = Tmp;
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[&](ArrayRef<unsigned> Regs) {
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MIRBuilder.buildMerge(VRegs[Idx], Regs);
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});
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if (Dst != VRegs[Idx])
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MIRBuilder.buildCopy(VRegs[Idx], Dst);
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Idx++;
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}
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@ -34,14 +34,15 @@ public:
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bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
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ArrayRef<unsigned> VRegs) const override;
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private:
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/// A function of this type is used to perform value split action.
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typedef std::function<void(unsigned, uint64_t)> SplitArgTy;
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typedef std::function<void(ArrayRef<unsigned>)> SplitArgTy;
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void splitToValueTypes(const ArgInfo &OrigArgInfo,
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SmallVectorImpl<ArgInfo> &SplitArgs,
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const DataLayout &DL, MachineRegisterInfo &MRI,
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SplitArgTy SplitArg) const;
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};
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} // End of namespace llvm;
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} // namespace llvm
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#endif
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133
test/CodeGen/X86/GlobalISel/callingconv.ll
Normal file
133
test/CodeGen/X86/GlobalISel/callingconv.ll
Normal file
@ -0,0 +1,133 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 --check-prefix=X32_GISEL
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; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 --check-prefix=X32_ISEL
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; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 --check-prefix=X64_GISEL
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; RUN: llc -mtriple=x86_64-linux-gnu < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 --check-prefix=X64_ISEL
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define i32 @test_ret_i32() {
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; X32-LABEL: test_ret_i32:
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; X32: # BB#0:
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; X32-NEXT: movl $20, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test_ret_i32:
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; X64: # BB#0:
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; X64-NEXT: movl $20, %eax
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; X64-NEXT: retq
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ret i32 20
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}
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define i64 @test_ret_i64() {
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; X32_GISEL-LABEL: test_ret_i64:
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; X32_GISEL: # BB#0:
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; X32_GISEL-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
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; X32_GISEL-NEXT: movl $15, %edx
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; X32_GISEL-NEXT: retl
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;
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; X32_ISEL-LABEL: test_ret_i64:
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; X32_ISEL: # BB#0:
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; X32_ISEL-NEXT: movl $-1, %eax
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; X32_ISEL-NEXT: movl $15, %edx
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; X32_ISEL-NEXT: retl
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;
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; X64-LABEL: test_ret_i64:
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; X64: # BB#0:
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; X64-NEXT: movabsq $68719476735, %rax # imm = 0xFFFFFFFFF
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; X64-NEXT: retq
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ret i64 68719476735
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}
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define i32 @test_arg_i32(i32 %a) {
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; X32_GISEL-LABEL: test_arg_i32:
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; X32_GISEL: # BB#0:
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; X32_GISEL-NEXT: leal 4(%esp), %eax
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; X32_GISEL-NEXT: movl (%eax), %eax
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; X32_GISEL-NEXT: retl
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;
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; X32_ISEL-LABEL: test_arg_i32:
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; X32_ISEL: # BB#0:
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; X32_ISEL-NEXT: movl 4(%esp), %eax
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; X32_ISEL-NEXT: retl
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;
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; X64-LABEL: test_arg_i32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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ret i32 %a
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}
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define i64 @test_arg_i64(i64 %a) {
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; X32_GISEL-LABEL: test_arg_i64:
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; X32_GISEL: # BB#0:
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; X32_GISEL-NEXT: leal 4(%esp), %eax
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; X32_GISEL-NEXT: movl (%eax), %eax
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; X32_GISEL-NEXT: leal 8(%esp), %ecx
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; X32_GISEL-NEXT: movl (%ecx), %edx
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; X32_GISEL-NEXT: retl
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;
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; X32_ISEL-LABEL: test_arg_i64:
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; X32_ISEL: # BB#0:
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; X32_ISEL-NEXT: movl 4(%esp), %eax
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; X32_ISEL-NEXT: movl 8(%esp), %edx
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; X32_ISEL-NEXT: retl
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;
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; X64-LABEL: test_arg_i64:
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; X64: # BB#0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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ret i64 %a
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}
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define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8) {
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; X32_GISEL-LABEL: test_i64_args_8:
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; X32_GISEL: # BB#0:
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; X32_GISEL-NEXT: leal 60(%esp), %eax
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; X32_GISEL-NEXT: movl (%eax), %eax
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; X32_GISEL-NEXT: leal 64(%esp), %ecx
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; X32_GISEL-NEXT: movl (%ecx), %edx
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; X32_GISEL-NEXT: retl
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;
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; X32_ISEL-LABEL: test_i64_args_8:
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; X32_ISEL: # BB#0:
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; X32_ISEL-NEXT: movl 60(%esp), %eax
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; X32_ISEL-NEXT: movl 64(%esp), %edx
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; X32_ISEL-NEXT: retl
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;
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; X64_GISEL-LABEL: test_i64_args_8:
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; X64_GISEL: # BB#0:
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; X64_GISEL-NEXT: leaq 16(%rsp), %rax
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; X64_GISEL-NEXT: movq (%rax), %rax
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; X64_GISEL-NEXT: retq
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;
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; X64_ISEL-LABEL: test_i64_args_8:
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; X64_ISEL: # BB#0:
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; X64_ISEL-NEXT: movq 16(%rsp), %rax
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; X64_ISEL-NEXT: retq
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ret i64 %arg8
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}
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define <4 x i32> @test_v4i32_args(<4 x i32> %arg1, <4 x i32> %arg2) {
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; X32-LABEL: test_v4i32_args:
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; X32: # BB#0:
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; X32-NEXT: movaps %xmm1, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_v4i32_args:
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; X64: # BB#0:
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; X64-NEXT: movaps %xmm1, %xmm0
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; X64-NEXT: retq
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ret <4 x i32> %arg2
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}
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define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) {
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; X32-LABEL: test_v8i32_args:
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; X32: # BB#0:
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; X32-NEXT: retl
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;
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; X64-LABEL: test_v8i32_args:
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; X64: # BB#0:
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; X64-NEXT: retq
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ret <8 x i32> %arg1
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}
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@ -207,24 +207,15 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
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; X32-NEXT: [[ARG8H_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK60]]
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; X32-NEXT: [[ARG8H:%[0-9]+]](s32) = G_LOAD [[ARG8H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK60]], align 0)
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; X32-NEXT: [[UNDEF:%[0-9]+]](s64) = IMPLICIT_DEF
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; X32-NEXT: [[ARG1_TMP0:%[0-9]+]](s64) = G_INSERT [[UNDEF]], [[ARG1L]](s32), 0
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; X32-NEXT: [[ARG1_TMP1:%[0-9]+]](s64) = G_INSERT [[ARG1_TMP0]], [[ARG1H]](s32), 32
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; X32-NEXT: [[ARG1:%[0-9]+]](s64) = COPY [[ARG1_TMP1]]
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; ... a bunch more that we don't track ...
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; X32: IMPLICIT_DEF
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; X32: IMPLICIT_DEF
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; X32: IMPLICIT_DEF
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; X32: IMPLICIT_DEF
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; X32: IMPLICIT_DEF
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; X32: [[UNDEF:%[0-9]+]](s64) = IMPLICIT_DEF
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; X32-NEXT: [[ARG7_TMP0:%[0-9]+]](s64) = G_INSERT [[UNDEF]], [[ARG7L]](s32), 0
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; X32-NEXT: [[ARG7_TMP1:%[0-9]+]](s64) = G_INSERT [[ARG7_TMP0]], [[ARG7H]](s32), 32
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; X32-NEXT: [[ARG7:%[0-9]+]](s64) = COPY [[ARG7_TMP1]]
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; X32-NEXT: [[UNDEF:%[0-9]+]](s64) = IMPLICIT_DEF
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; X32-NEXT: [[ARG8_TMP0:%[0-9]+]](s64) = G_INSERT [[UNDEF]], [[ARG8L]](s32), 0
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; X32-NEXT: [[ARG8_TMP1:%[0-9]+]](s64) = G_INSERT [[ARG8_TMP0]], [[ARG8H]](s32), 32
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; X32-NEXT: [[ARG8:%[0-9]+]](s64) = COPY [[ARG8_TMP1]]
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; X32-NEXT: [[ARG1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARG1L]](s32), [[ARG1H]](s32)
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; ... a bunch more that we don't track ...
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; X32-NEXT: G_MERGE_VALUES
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; X32-NEXT: G_MERGE_VALUES
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; X32-NEXT: G_MERGE_VALUES
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; X32-NEXT: G_MERGE_VALUES
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; X32-NEXT: G_MERGE_VALUES
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; X32-NEXT: [[ARG7:%[0-9]+]](s64) = G_MERGE_VALUES [[ARG7L]](s32), [[ARG7H]](s32)
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; X32-NEXT: [[ARG8:%[0-9]+]](s64) = G_MERGE_VALUES [[ARG8L]](s32), [[ARG8H]](s32)
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; ALL-NEXT: [[GADDR_A1:%[0-9]+]](p0) = G_GLOBAL_VALUE @a1_64bit
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; ALL-NEXT: [[GADDR_A7:%[0-9]+]](p0) = G_GLOBAL_VALUE @a7_64bit
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@ -236,8 +227,7 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
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; X64-NEXT: %rax = COPY [[ARG1]](s64)
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; X64-NEXT: RET 0, implicit %rax
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; X32-NEXT: [[RETL:%[0-9]+]](s32) = G_EXTRACT [[ARG1:%[0-9]+]](s64), 0
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; X32-NEXT: [[RETH:%[0-9]+]](s32) = G_EXTRACT [[ARG1:%[0-9]+]](s64), 32
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; X32-NEXT: [[RETL:%[0-9]+]](s32), [[RETH:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](s64)
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; X32-NEXT: %eax = COPY [[RETL:%[0-9]+]](s32)
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; X32-NEXT: %edx = COPY [[RETH:%[0-9]+]](s32)
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; X32-NEXT: RET 0, implicit %eax, implicit %edx
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@ -15,12 +15,8 @@ define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) {
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; X64: liveins: %xmm0, %xmm1
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; X64: [[ARG1L:%[0-9]+]](<4 x s32>) = COPY %xmm0
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; X64-NEXT: [[ARG1H:%[0-9]+]](<4 x s32>) = COPY %xmm1
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; X64-NEXT: [[UNDEF:%[0-9]+]](<8 x s32>) = IMPLICIT_DEF
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; X64-NEXT: [[ARG1_TMP0:%[0-9]+]](<8 x s32>) = G_INSERT [[UNDEF]], [[ARG1L]](<4 x s32>), 0
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; X64-NEXT: [[ARG1_TMP1:%[0-9]+]](<8 x s32>) = G_INSERT [[ARG1_TMP0]], [[ARG1H]](<4 x s32>), 128
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; X64-NEXT: [[ARG1:%[0-9]+]](<8 x s32>) = COPY [[ARG1_TMP1]]
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; X64-NEXT: [[RETL:%[0-9]+]](<4 x s32>) = G_EXTRACT [[ARG1:%[0-9]+]](<8 x s32>), 0
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; X64-NEXT: [[RETH:%[0-9]+]](<4 x s32>) = G_EXTRACT [[ARG1:%[0-9]+]](<8 x s32>), 128
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; X64-NEXT: [[ARG1:%[0-9]+]](<8 x s32>) = G_MERGE_VALUES [[ARG1L]](<4 x s32>), [[ARG1H]](<4 x s32>)
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; X64-NEXT: [[RETL:%[0-9]+]](<4 x s32>), [[RETH:%[0-9]+]](<4 x s32>) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](<8 x s32>)
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; X64-NEXT: %xmm0 = COPY [[RETL:%[0-9]+]](<4 x s32>)
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; X64-NEXT: %xmm1 = COPY [[RETH:%[0-9]+]](<4 x s32>)
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; X64-NEXT: RET 0, implicit %xmm0, implicit %xmm1
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