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Use the relationship models infrastructure to add two relations - getPredOpcode
and getPredNewOpcode. The first relates non predicated instructions with their predicated forms and the second relates predicated instructions with their predicate-new forms. Patch by Jyotsna Verma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pranav Bhandarkar
parent
938482f522
commit
8aa138c122
@ -56,6 +56,16 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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bits<1> isPredicated = 0;
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let TSFlags{6} = isPredicated;
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// Dot new value store instructions.
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bits<1> isNVStore = 0;
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let TSFlags{8} = isNVStore;
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// Fields used for relation models.
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string BaseOpcode = "";
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string CextOpcode = "";
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string PredSense = "";
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string PNewValue = "";
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string InputType = ""; // Input is "imm" or "reg" type.
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// *** The code above must match HexagonBaseInfo.h ***
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}
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@ -25,6 +25,7 @@
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/MathExtras.h"
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#define GET_INSTRINFO_CTOR
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#define GET_INSTRMAP_INFO
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#include "HexagonGenInstrInfo.inc"
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#include "HexagonGenDFAPacketizer.inc"
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@ -1915,6 +1916,15 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
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int HexagonInstrInfo::
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getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
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enum Hexagon::PredSense inPredSense;
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inPredSense = invertPredicate ? Hexagon::PredSense_false :
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Hexagon::PredSense_true;
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int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
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if (CondOpcode >= 0) // Valid Conditional opcode/instruction
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return CondOpcode;
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// This switch case will be removed once all the instructions have been
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// modified to use relation maps.
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switch(Opc) {
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case Hexagon::TFR:
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return !invertPredicate ? Hexagon::TFR_cPt :
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@ -1934,24 +1944,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
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case Hexagon::JMP_EQriPt_nv_V4:
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return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
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Hexagon::JMP_EQriNotPt_nv_V4;
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case Hexagon::ADD_ri:
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return !invertPredicate ? Hexagon::ADD_ri_cPt :
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Hexagon::ADD_ri_cNotPt;
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case Hexagon::ADD_rr:
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return !invertPredicate ? Hexagon::ADD_rr_cPt :
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Hexagon::ADD_rr_cNotPt;
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case Hexagon::XOR_rr:
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return !invertPredicate ? Hexagon::XOR_rr_cPt :
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Hexagon::XOR_rr_cNotPt;
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case Hexagon::AND_rr:
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return !invertPredicate ? Hexagon::AND_rr_cPt :
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Hexagon::AND_rr_cNotPt;
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case Hexagon::OR_rr:
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return !invertPredicate ? Hexagon::OR_rr_cPt :
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Hexagon::OR_rr_cNotPt;
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case Hexagon::SUB_rr:
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return !invertPredicate ? Hexagon::SUB_rr_cPt :
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Hexagon::SUB_rr_cNotPt;
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case Hexagon::COMBINE_rr:
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return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
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Hexagon::COMBINE_rr_cNotPt;
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@ -14,6 +14,18 @@
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include "HexagonInstrFormats.td"
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include "HexagonImmediates.td"
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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// PredRel - Filter class used to relate non-predicated instructions with their
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// predicated forms.
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class PredRel;
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// PredNewRel - Filter class used to relate predicated instructions with their
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// predicate-new forms.
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class PredNewRel: PredRel;
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// ImmRegRel - Filter class used to relate instructions having reg-reg form
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// with their reg-imm counterparts.
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class ImmRegRel;
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//===----------------------------------------------------------------------===//
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// Hexagon Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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@ -148,37 +160,91 @@ multiclass CMP32_ri_s8<string OpcStr, PatFrag OpNode> {
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}
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//===----------------------------------------------------------------------===//
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// ALU32/ALU +
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// ALU32/ALU (Instructions with register-register form)
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//===----------------------------------------------------------------------===//
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// Add.
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let isCommutable = 1, isPredicable = 1 in
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def ADD_rr : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = add($src1, $src2)",
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[(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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multiclass ALU32_Pbase<string mnemonic, bit isNot,
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bit isPredNew> {
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let isPredicable = 1 in
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def ADD_ri : ALU32_ri<(outs IntRegs:$dst),
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
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") $dst = ")#mnemonic#"($src2, $src3)",
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[]>;
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}
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multiclass ALU32_Pred<string mnemonic, bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
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}
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}
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let InputType = "reg" in
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multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
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let isPredicable = 1 in
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def #NAME# : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = "#mnemonic#"($src1, $src2)",
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[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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let neverHasSideEffects = 1, isPredicated = 1 in {
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defm Pt : ALU32_Pred<mnemonic, 0>;
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defm NotPt : ALU32_Pred<mnemonic, 1>;
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}
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}
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}
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let isCommutable = 1 in {
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defm ADD_rr : ALU32_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
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defm AND_rr : ALU32_base<"and", "AND", and>, ImmRegRel, PredNewRel;
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defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel;
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defm OR_rr : ALU32_base<"or", "OR", or>, ImmRegRel, PredNewRel;
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}
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defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel;
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//===----------------------------------------------------------------------===//
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// ALU32/ALU (ADD with register-immediate form)
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//===----------------------------------------------------------------------===//
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multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Imm: $src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
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") $dst = ")#mnemonic#"($src2, #$src3)",
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[]>;
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}
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multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
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}
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}
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let InputType = "imm" in
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multiclass ALU32ri_base<string mnemonic, string CextOp, SDNode OpNode> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
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let isPredicable = 1 in
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def #NAME# : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s16Imm:$src2),
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"$dst = add($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (add (i32 IntRegs:$src1),
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s16ImmPred:$src2))]>;
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"$dst = "#mnemonic#"($src1, #$src2)",
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[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
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(s16ImmPred:$src2)))]>;
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// Logical operations.
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let isPredicable = 1 in
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def XOR_rr : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = xor($src1, $src2)",
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[(set (i32 IntRegs:$dst), (xor (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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let neverHasSideEffects = 1, isPredicated = 1 in {
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defm Pt : ALU32ri_Pred<mnemonic, 0>;
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defm NotPt : ALU32ri_Pred<mnemonic, 1>;
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}
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}
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}
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let isCommutable = 1, isPredicable = 1 in
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def AND_rr : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = and($src1, $src2)",
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[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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defm ADD_ri : ALU32ri_base<"add", "ADD", add>, ImmRegRel, PredNewRel;
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def OR_ri : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s10Imm:$src2),
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@ -197,13 +263,6 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst),
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[(set (i32 IntRegs:$dst), (and (i32 IntRegs:$src1),
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s10ImmPred:$src2))]>;
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let isCommutable = 1, isPredicable = 1 in
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def OR_rr : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = or($src1, $src2)",
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[(set (i32 IntRegs:$dst), (or (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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// Negate.
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def NEG : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = neg($src1)",
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@ -214,14 +273,6 @@ def NOP : ALU32_rr<(outs), (ins),
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"nop",
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[]>;
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// Subtract.
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let isPredicable = 1 in
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def SUB_rr : ALU32_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = sub($src1, $src2)",
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[(set (i32 IntRegs:$dst), (sub (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))]>;
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// Rd32=sub(#s10,Rs32)
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def SUB_ri : ALU32_ri<(outs IntRegs:$dst),
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(ins s10Imm:$src1, IntRegs:$src2),
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@ -348,56 +399,6 @@ def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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// ALU32/PRED +
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//===----------------------------------------------------------------------===//
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// Conditional add.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
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"if ($src1) $dst = add($src2, #$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
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"if (!$src1) $dst = add($src2, #$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
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"if ($src1.new) $dst = add($src2, #$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, s8Imm:$src3),
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"if (!$src1.new) $dst = add($src2, #$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst = add($src2, $src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst = add($src2, $src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst = add($src2, $src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst = add($src2, $src3)",
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[]>;
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// Conditional combine.
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let neverHasSideEffects = 1, isPredicated = 1 in
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@ -424,108 +425,6 @@ def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst),
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"if (!$src1.new) $dst = combine($src2, $src3)",
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[]>;
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// Conditional logical operations.
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let isPredicated = 1 in
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def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst = xor($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst = xor($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst = xor($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst = xor($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst = and($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst = and($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst = and($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst = and($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst = or($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst = or($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst = or($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst = or($src2, $src3)",
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[]>;
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// Conditional subtract.
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let isPredicated = 1 in
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def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst = sub($src2, $src3)",
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[]>;
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let isPredicated = 1 in
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def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst = sub($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst = sub($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
let isPredicated = 1 in
|
||||
def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst = sub($src2, $src3)",
|
||||
[]>;
|
||||
|
||||
|
||||
// Conditional transfer.
|
||||
let neverHasSideEffects = 1, isPredicated = 1 in
|
||||
def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2),
|
||||
@ -3546,4 +3445,31 @@ include "HexagonInstrInfoV5.td"
|
||||
// V5 Instructions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Generate mapping table to relate non-predicate instructions with their
|
||||
// predicated formats - true and false.
|
||||
//
|
||||
|
||||
def getPredOpcode : InstrMapping {
|
||||
let FilterClass = "PredRel";
|
||||
// Instructions with the same BaseOpcode and isNVStore values form a row.
|
||||
let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
|
||||
// Instructions with the same predicate sense form a column.
|
||||
let ColFields = ["PredSense"];
|
||||
// The key column is the unpredicated instructions.
|
||||
let KeyCol = [""];
|
||||
// Value columns are PredSense=true and PredSense=false
|
||||
let ValueCols = [["true"], ["false"]];
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Generate mapping table to relate predicated instructions with their .new
|
||||
// format.
|
||||
//
|
||||
def getPredNewOpcode : InstrMapping {
|
||||
let FilterClass = "PredNewRel";
|
||||
let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
|
||||
let ColFields = ["PNewValue"];
|
||||
let KeyCol = [""];
|
||||
let ValueCols = [["new"]];
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user