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[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors

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Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE
unpredicated ADD/SUB instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39087


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Florian Hahn 2017-11-07 10:43:56 +00:00
parent b79469ca2f
commit 8aa5d0fb6a
1 changed files with 5 additions and 0 deletions
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5
utils/TableGen/CodeGenDAGPatterns.cpp
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@ -603,6 +603,11 @@ bool TypeInfer::EnforceVectorSubVectorTypeIs(TypeSetByHwMode &Vec,
auto IsSubVec = [](MVT B, MVT P) -> bool {
if (!B.isVector() || !P.isVector())
return false;
// Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
// but until there are obvious use-cases for this, keep the
// types separate.
if (B.isScalableVector() != P.isScalableVector())
return false;
if (B.getVectorElementType() != P.getVectorElementType())
return false;
return B.getVectorNumElements() < P.getVectorNumElements();