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- Move conversion of [SU]ADDO from DAG combiner into legalizer.

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- Add "promote integer type" stuff to the legalizer for these nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59847 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-11-22 00:22:52 +00:00
parent 50cacb2a52
commit 8ac0d4b4fb
4 changed files with 53 additions and 38 deletions
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34
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -190,8 +190,6 @@ namespace {
SDValue visitBUILD_VECTOR(SDNode *N);
SDValue visitCONCAT_VECTORS(SDNode *N);
SDValue visitVECTOR_SHUFFLE(SDNode *N);
SDValue visitSADDO(SDNode *N);
SDValue visitUADDO(SDNode *N);
SDValue XformToShuffleWithZero(SDNode *N);
SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
@ -729,8 +727,6 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
case ISD::SADDO: return visitSADDO(N);
case ISD::UADDO: return visitUADDO(N);
}
return SDValue();
}
@ -5147,36 +5143,6 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
return SDValue();
}
SDValue DAGCombiner::visitSADDO(SDNode *N) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
AddToWorkList(Sum.getNode());
SDValue Cmp = DAG.getSetCC(MVT::i1, Sum, LHS, ISD::SETLT);
AddToWorkList(Cmp.getNode());
MVT ValueVTs[] = { LHS.getValueType(), MVT::i1 };
SDValue Ops[] = { Sum, Cmp };
SDValue Merge = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2),
&Ops[0], 2);
SDNode *MNode = Merge.getNode();
AddToWorkList(MNode);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(MNode, 0));
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(MNode, 1));
// Since the node is now dead, remove it from the graph.
removeFromWorkList(N);
DAG.DeleteNode(N);
return SDValue(N, 0);
}
SDValue DAGCombiner::visitUADDO(SDNode *N) {
return visitSADDO(N);
}
/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
/// an AND to a vector_shuffle with the destination vector and a zero vector.
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>

21
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -4167,6 +4167,27 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
}
break;
}
case ISD::SADDO: {
SDValue LHS = LegalizeOp(Node->getOperand(0));
SDValue RHS = LegalizeOp(Node->getOperand(1));
SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
MVT OType = SDValue(Node, 1).getValueType();
SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, ISD::SETLT);
MVT ValueVTs[] = { LHS.getValueType(), OType };
SDValue Ops[] = { Sum, Cmp };
Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
SDNode *RNode = Result.getNode();
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
break;
}
case ISD::UADDO: {
break;
}
}
assert(Result.getValueType() == Op.getValueType() &&

33
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -84,20 +84,23 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
case ISD::AND:
case ISD::OR:
case ISD::XOR:
case ISD::ADD:
case ISD::SUB:
case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
case ISD::SDIV:
case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
case ISD::UDIV:
case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
case ISD::SADDO: Result = PromoteIntRes_SADDO(N, ResNo); break;
case ISD::UADDO: Result = PromoteIntRes_UADDO(N, ResNo); break;
case ISD::ATOMIC_LOAD_ADD_8:
case ISD::ATOMIC_LOAD_SUB_8:
@ -515,6 +518,28 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
SDValue DAGTypeLegalizer::PromoteIntRes_XADDO(SDNode *N, unsigned ResNo,
ISD::NodeType NTy) {
MVT NewVT = TLI.getTypeToTransformTo(SDValue(N, ResNo).getValueType());
assert(isTypeLegal(NewVT) && "Illegal XADDO type!");
MVT ValueVTs[] = { N->getOperand(0).getValueType(), NewVT };
SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
SDValue Res = DAG.getNode(NTy, DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
ReplaceValueWith(SDValue(N, 0), SDValue(Res.getNode(), 0));
ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
return Res;
}
SDValue DAGTypeLegalizer::PromoteIntRes_SADDO(SDNode *N, unsigned ResNo) {
return PromoteIntRes_XADDO(N, ResNo, ISD::SADDO);
}
SDValue DAGTypeLegalizer::PromoteIntRes_UADDO(SDNode *N, unsigned ResNo) {
return PromoteIntRes_XADDO(N, ResNo, ISD::UADDO);
}
SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
}

3
lib/CodeGen/SelectionDAG/LegalizeTypes.h
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@ -268,6 +268,9 @@ private:
SDValue PromoteIntRes_SRL(SDNode *N);
SDValue PromoteIntRes_TRUNCATE(SDNode *N);
SDValue PromoteIntRes_UDIV(SDNode *N);
SDValue PromoteIntRes_XADDO(SDNode *N, unsigned ResNo, ISD::NodeType NTy);
SDValue PromoteIntRes_SADDO(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_UADDO(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_UNDEF(SDNode *N);
SDValue PromoteIntRes_VAARG(SDNode *N);