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[ARM] GlobalISel: Add reg mapping for s64 G_FCMP

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Map the result into GPR and the operands into FPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307653 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus 2017-07-11 11:47:45 +00:00
parent eb75f906da
commit 8ae39dc847
2 changed files with 38 additions and 5 deletions
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14
lib/Target/ARM/ARMRegisterBankInfo.cpp
View File

@ -279,16 +279,20 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
case G_FCMP: {
LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
(void)Ty1;
LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
(void)Ty2;
assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
assert(Ty1.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
"Mismatched operand sizes for G_FCMP");
unsigned Size = Ty1.getSizeInBits();
assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
: &ARM::ValueMappings[ARM::DPR3OpsIdx];
OperandsMapping =
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
&ARM::ValueMappings[ARM::SPR3OpsIdx],
&ARM::ValueMappings[ARM::SPR3OpsIdx]});
FPRValueMapping, FPRValueMapping});
break;
}
case G_MERGE_VALUES: {

29
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -36,6 +36,7 @@
define void @test_icmp_eq_s32() { ret void }
define void @test_fcmp_one_s32() #0 { ret void }
define void @test_fcmp_ugt_s64() #0 { ret void }
define void @test_select_s32() { ret void }
@ -770,6 +771,34 @@ body: |
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_ugt_s64
# CHECK-LABEL: name: test_fcmp_ugt_s64
legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0:
liveins: %d0, %d1
%0(s64) = COPY %d0
%1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0
...
---
name: test_select_s32