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[ARM] Enable the use of SVC anywhere in an IT block

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Differential Revision: https://reviews.llvm.org/D37374


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312908 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andre Vieira 2017-09-11 11:11:17 +00:00
parent 9942f5143c
commit 8bb02cf4a4
2 changed files with 10 additions and 3 deletions
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7
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -8717,9 +8717,10 @@ template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
// All branch & call instructions terminate IT blocks.
if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() ||
MCID.isBranch() || MCID.isIndirectBranch())
// All branch & call instructions terminate IT blocks with the exception of
// SVC.
if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
return true;
// Any arithmetic instruction which writes to the PC also terminates the IT

6
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -3113,12 +3113,18 @@ _func:
svceq #255
it ne
swine #33
itt eq
svceq #0
svceq #1
@ CHECK: svc #0 @ encoding: [0x00,0xdf]
@ CHECK: it eq @ encoding: [0x08,0xbf]
@ CHECK: svceq #255 @ encoding: [0xff,0xdf]
@ CHECK: it ne @ encoding: [0x18,0xbf]
@ CHECK: svcne #33 @ encoding: [0x21,0xdf]
@ CHECK: itt eq @ encoding: [0x04,0xbf]
@ CHECK: svceq #0 @ encoding: [0x00,0xdf]
@ CHECK: svceq #1 @ encoding: [0x01,0xdf]
@------------------------------------------------------------------------------