RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-04-15 04:20:27 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Get Triple::getARMCPUForArch() to use TargetParser

Browse Source 
First ARMTargetParser FIXME, conservatively changing the way we parse CPUs
in the back-end. Still not perfect, with a lot of special cases, but moving
towards a more generic solution.

Moving all logic to the target parser made some unwritten assumptions
about architectures in Clang to break. I've added a lot of architectures
required by Clang, and default to CPUs that Clang believes it should
(and I agree).

I've also added a lot of unit tests, with the correct CPU for each
architecture, and Clang seems to be working correctly, too.

It also became clear that using "unsigned ID" as the argument for the get
methods makes it hard to know what ID, so I also changed the argument names
to match the enum type names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2015-05-20 15:05:07 +00:00
parent 5a2d715235
commit 8ca7ac2a38
4 changed files with 367 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
include/llvm/Support/TargetParser.h
View File

@ -69,8 +69,16 @@ namespace ARM {
AK_ARMV7M, AK_ARMV7M,
AK_ARMV8A, AK_ARMV8A,
AK_ARMV8_1A, AK_ARMV8_1A,
// Non-standard Arch names.
AK_IWMMXT, AK_IWMMXT,
AK_IWMMXT2, AK_IWMMXT2,
AK_XSCALE,
AK_ARMV5E,
AK_ARMV5TEJ,
AK_ARMV6SM,
AK_ARMV7L,
AK_ARMV7S,
AK_ARMV7EM,
AK_LAST AK_LAST
}; };
@ -95,17 +103,21 @@ class ARMTargetParser {
static StringRef getArchSynonym(StringRef Arch); static StringRef getArchSynonym(StringRef Arch);
public: public:
static StringRef getCanonicalArchName(StringRef Arch);
// Information by ID // Information by ID
static const char * getFPUName(unsigned ID); static const char * getFPUName(unsigned FPUKind);
static const char * getArchName(unsigned ID); static const char * getArchName(unsigned ArchKind);
static unsigned getArchDefaultCPUArch(unsigned ID); static unsigned getArchDefaultCPUArch(unsigned ArchKind);
static const char * getArchDefaultCPUName(unsigned ID); static const char * getArchDefaultCPUName(unsigned ArchKind);
static const char * getArchExtName(unsigned ID); static const char * getArchExtName(unsigned ArchExtKind);
static const char * getDefaultCPU(StringRef Arch);
// Parser // Parser
static unsigned parseFPU(StringRef FPU); static unsigned parseFPU(StringRef FPU);
static unsigned parseArch(StringRef Arch); static unsigned parseArch(StringRef Arch);
static unsigned parseArchExt(StringRef ArchExt); static unsigned parseArchExt(StringRef ArchExt);
static unsigned parseCPUArch(StringRef CPU);
}; };
} // namespace llvm } // namespace llvm

203
lib/Support/TargetParser.cpp
View File

@ -73,8 +73,16 @@ struct {
{ "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 }, { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
{ "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 }, { "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
{ "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 }, { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
// Non-standard Arch names.
{ "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE }, { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
{ "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE } { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE },
{ "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE },
{ "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE },
{ "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE },
{ "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M },
{ "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
{ "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 },
{ "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 }
}; };
// List of canonical ARCH names (use getARCHSynonym) // List of canonical ARCH names (use getARCHSynonym)
// FIXME: TableGen this. // FIXME: TableGen this.
@ -91,6 +99,92 @@ struct {
{ "sec", ARM::AEK_SEC }, { "sec", ARM::AEK_SEC },
{ "virt", ARM::AEK_VIRT } { "virt", ARM::AEK_VIRT }
}; };
// List of CPU names and their arches.
// The same CPU can have multiple arches and can be default on multiple arches.
// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
// FIXME: TableGen this.
struct {
const char *Name;
ARM::ArchKind ArchID;
bool Default;
} CPUNames[] = {
{ "arm2", ARM::AK_ARMV2, true },
{ "arm6", ARM::AK_ARMV3, true },
{ "arm7m", ARM::AK_ARMV3M, true },
{ "strongarm", ARM::AK_ARMV4, true },
{ "arm7tdmi", ARM::AK_ARMV4T, true },
{ "arm7tdmi-s", ARM::AK_ARMV4T, false },
{ "arm710t", ARM::AK_ARMV4T, false },
{ "arm720t", ARM::AK_ARMV4T, false },
{ "arm9", ARM::AK_ARMV4T, false },
{ "arm9tdmi", ARM::AK_ARMV4T, false },
{ "arm920", ARM::AK_ARMV4T, false },
{ "arm920t", ARM::AK_ARMV4T, false },
{ "arm922t", ARM::AK_ARMV4T, false },
{ "arm9312", ARM::AK_ARMV4T, false },
{ "arm940t", ARM::AK_ARMV4T, false },
{ "ep9312", ARM::AK_ARMV4T, false },
{ "arm10tdmi", ARM::AK_ARMV5, true },
{ "arm10tdmi", ARM::AK_ARMV5T, true },
{ "arm1020t", ARM::AK_ARMV5T, false },
{ "xscale", ARM::AK_XSCALE, true },
{ "xscale", ARM::AK_ARMV5TE, false },
{ "arm9e", ARM::AK_ARMV5TE, false },
{ "arm926ej-s", ARM::AK_ARMV5TE, false },
{ "arm946ej-s", ARM::AK_ARMV5TE, false },
{ "arm966e-s", ARM::AK_ARMV5TE, false },
{ "arm968e-s", ARM::AK_ARMV5TE, false },
{ "arm1020e", ARM::AK_ARMV5TE, false },
{ "arm1022e", ARM::AK_ARMV5TE, true },
{ "iwmmxt", ARM::AK_ARMV5TE, false },
{ "iwmmxt", ARM::AK_IWMMXT, true },
{ "arm1136jf-s", ARM::AK_ARMV6, true },
{ "arm1136j-s", ARM::AK_ARMV6J, true },
{ "arm1136jz-s", ARM::AK_ARMV6J, false },
{ "arm1176j-s", ARM::AK_ARMV6K, false },
{ "mpcore", ARM::AK_ARMV6K, false },
{ "mpcorenovfp", ARM::AK_ARMV6K, false },
{ "arm1176jzf-s", ARM::AK_ARMV6K, true },
{ "arm1176jzf-s", ARM::AK_ARMV6Z, true },
{ "arm1176jzf-s", ARM::AK_ARMV6ZK, true },
{ "arm1156t2-s", ARM::AK_ARMV6T2, true },
{ "arm1156t2f-s", ARM::AK_ARMV6T2, false },
{ "cortex-m0", ARM::AK_ARMV6M, true },
{ "cortex-m0plus", ARM::AK_ARMV6M, false },
{ "cortex-m1", ARM::AK_ARMV6M, false },
{ "sc000", ARM::AK_ARMV6M, false },
{ "cortex-a8", ARM::AK_ARMV7, true },
{ "cortex-a5", ARM::AK_ARMV7A, false },
{ "cortex-a7", ARM::AK_ARMV7A, false },
{ "cortex-a8", ARM::AK_ARMV7A, true },
{ "cortex-a9", ARM::AK_ARMV7A, false },
{ "cortex-a12", ARM::AK_ARMV7A, false },
{ "cortex-a15", ARM::AK_ARMV7A, false },
{ "cortex-a17", ARM::AK_ARMV7A, false },
{ "krait", ARM::AK_ARMV7A, false },
{ "cortex-r4", ARM::AK_ARMV7R, true },
{ "cortex-r4f", ARM::AK_ARMV7R, false },
{ "cortex-r5", ARM::AK_ARMV7R, false },
{ "cortex-r7", ARM::AK_ARMV7R, false },
{ "sc300", ARM::AK_ARMV7M, false },
{ "cortex-m3", ARM::AK_ARMV7M, true },
{ "cortex-m4", ARM::AK_ARMV7M, false },
{ "cortex-m7", ARM::AK_ARMV7M, false },
{ "cortex-a53", ARM::AK_ARMV8A, true },
{ "cortex-a57", ARM::AK_ARMV8A, false },
{ "cortex-a72", ARM::AK_ARMV8A, false },
{ "cyclone", ARM::AK_ARMV8A, false },
{ "generic", ARM::AK_ARMV8_1A, true },
// Non-standard Arch names.
{ "arm1022e", ARM::AK_ARMV5E, true },
{ "arm926ej-s", ARM::AK_ARMV5TEJ, true },
{ "cortex-m0", ARM::AK_ARMV6SM, true },
{ "cortex-a8", ARM::AK_ARMV7L, true },
{ "cortex-m4", ARM::AK_ARMV7EM, true },
{ "swift", ARM::AK_ARMV7S, true },
// Invalid CPU
{ "invalid", ARM::AK_INVALID, true }
};
} // namespace } // namespace
@ -100,34 +194,47 @@ namespace llvm {
// Information by ID // Information by ID
// ======================================================= // // ======================================================= //
const char *ARMTargetParser::getFPUName(unsigned ID) { const char *ARMTargetParser::getFPUName(unsigned FPUKind) {
if (ID >= ARM::FK_LAST) if (FPUKind >= ARM::FK_LAST)
return nullptr; return nullptr;
return FPUNames[ID].Name; return FPUNames[FPUKind].Name;
} }
const char *ARMTargetParser::getArchName(unsigned ID) { const char *ARMTargetParser::getArchName(unsigned ArchKind) {
if (ID >= ARM::AK_LAST) if (ArchKind >= ARM::AK_LAST)
return nullptr; return nullptr;
return ARCHNames[ID].Name; return ARCHNames[ArchKind].Name;
} }
const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) { const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) {
if (ID >= ARM::AK_LAST) if (ArchKind >= ARM::AK_LAST)
return nullptr; return nullptr;
return ARCHNames[ID].DefaultCPU; return ARCHNames[ArchKind].DefaultCPU;
} }
unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) { unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) {
if (ID >= ARM::AK_LAST) if (ArchKind >= ARM::AK_LAST)
return 0; return ARMBuildAttrs::CPUArch::Pre_v4;
return ARCHNames[ID].DefaultArch; return ARCHNames[ArchKind].DefaultArch;
} }
const char *ARMTargetParser::getArchExtName(unsigned ID) { const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) {
if (ID >= ARM::AEK_LAST) if (ArchExtKind >= ARM::AEK_LAST)
return nullptr; return nullptr;
return ARCHExtNames[ID].Name; return ARCHExtNames[ArchExtKind].Name;
}
const char *ARMTargetParser::getDefaultCPU(StringRef Arch) {
unsigned AK = parseArch(Arch);
if (AK == ARM::AK_INVALID)
return nullptr;
// Look for multiple AKs to find the default for pair AK+Name.
for (const auto CPU : CPUNames) {
if (CPU.ArchID == AK && CPU.Default)
return CPU.Name;
}
return nullptr;
} }
// ======================================================= // // ======================================================= //
@ -154,16 +261,53 @@ StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) {
StringRef ARMTargetParser::getArchSynonym(StringRef Arch) { StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
return StringSwitch<StringRef>(Arch) return StringSwitch<StringRef>(Arch)
.Case("armv5tej", "armv5te") .Cases("armv6m", "v6m", "armv6-m")
.Case("armv6m", "armv6-m") .Cases("armv7a", "v7a", "armv7-a")
.Case("armv7a", "armv7-a") .Cases("armv7r", "v7r", "armv7-r")
.Case("armv7r", "armv7-r") .Cases("armv7m", "v7m", "armv7-m")
.Case("armv7m", "armv7-m") .Cases("armv7em", "v7em", "armv7e-m")
.Case("armv8a", "armv8-a") .Cases("armv8", "v8", "armv8-a")
.Case("armv8.1a", "armv8.1-a") .Cases("armv8a", "v8a", "armv8-a")
.Cases("armv8.1a", "v8.1a", "armv8.1-a")
.Default(Arch); .Default(Arch);
} }
// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
// "v.+", if the latter, return unmodified string. If invalid, return "".
StringRef ARMTargetParser::getCanonicalArchName(StringRef Arch) {
size_t offset = StringRef::npos;
StringRef A = Arch;
// Begins with "arm" / "thumb", move past it.
if (A.startswith("arm"))
offset = 3;
else if (A.startswith("thumb"))
offset = 5;
// Ex. "armebv7", move past the "eb".
if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
offset += 2;
// Or, if it ends with eb ("armv7eb"), chop it off.
else if (A.endswith("eb"))
A = A.substr(0, A.size() - 2);
// Reached the end or a 'v', canonicalise.
if (offset != StringRef::npos && (offset == A.size() || A[offset] == 'v'))
A = A.substr(offset);
// Empty string mans offset reached the end. Although valid, this arch
// will not have a match in the table. Return the original string.
if (A.empty())
return Arch;
// If can't find the arch, return an empty StringRef.
if (parseArch(A) == ARM::AK_INVALID)
A = A.substr(A.size());
// Arch will either be a 'v' name (v7a) or a marketing name (xscale)
// or empty, if invalid.
return A;
}
unsigned ARMTargetParser::parseFPU(StringRef FPU) { unsigned ARMTargetParser::parseFPU(StringRef FPU) {
StringRef Syn = getFPUSynonym(FPU); StringRef Syn = getFPUSynonym(FPU);
for (const auto F : FPUNames) { for (const auto F : FPUNames) {
@ -173,10 +317,11 @@ unsigned ARMTargetParser::parseFPU(StringRef FPU) {
return ARM::FK_INVALID; return ARM::FK_INVALID;
} }
// Allows partial match, ex. "v7a" matches "armv7a".
unsigned ARMTargetParser::parseArch(StringRef Arch) { unsigned ARMTargetParser::parseArch(StringRef Arch) {
StringRef Syn = getArchSynonym(Arch); StringRef Syn = getArchSynonym(Arch);
for (const auto A : ARCHNames) { for (const auto A : ARCHNames) {
if (Syn == A.Name) if (StringRef(A.Name).endswith(Syn))
return A.ID; return A.ID;
} }
return ARM::AK_INVALID; return ARM::AK_INVALID;
@ -190,4 +335,12 @@ unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
return ARM::AEK_INVALID; return ARM::AEK_INVALID;
} }
unsigned ARMTargetParser::parseCPUArch(StringRef CPU) {
for (const auto C : CPUNames) {
if (CPU == C.Name)
return C.ArchID;
}
return ARM::AK_INVALID;
}
} // namespace llvm } // namespace llvm

100
lib/Support/Triple.cpp
View File

@ -12,6 +12,7 @@
#include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetParser.h"
#include <cstring> #include <cstring>
using namespace llvm; using namespace llvm;
@ -1080,9 +1081,11 @@ const char *Triple::getARMCPUForArch(StringRef MArch) const {
if (MArch.empty()) if (MArch.empty())
MArch = getArchName(); MArch = getArchName();
// Some defaults are forced.
switch (getOS()) { switch (getOS()) {
case llvm::Triple::FreeBSD: case llvm::Triple::FreeBSD:
case llvm::Triple::NetBSD: case llvm::Triple::NetBSD:
// FIXME: This doesn't work on BE/thumb variants.
if (MArch == "armv6") if (MArch == "armv6")
return "arm1176jzf-s"; return "arm1176jzf-s";
break; break;
@ -1093,77 +1096,38 @@ const char *Triple::getARMCPUForArch(StringRef MArch) const {
break; break;
} }
// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)? MArch = ARMTargetParser::getCanonicalArchName(MArch);
// Only the (v.+) part is relevant for determining the CPU, as it determines if (MArch.empty())
// the architecture version, so we first remove the surrounding parts. return nullptr;
// (ep9312|iwmmxt|xscale)(eb)? is also permitted, so we have to be a bit
// careful when removing the leading (arm|thumb)?(eb)? as we don't want to
// permit things like armep9312.
const char *result = nullptr;
size_t offset = StringRef::npos;
if (MArch.startswith("arm"))
offset = 3;
else if (MArch.startswith("thumb"))
offset = 5;
if (offset != StringRef::npos && MArch.substr(offset, 2) == "eb")
offset += 2;
else if (MArch.endswith("eb"))
MArch = MArch.substr(0, MArch.size() - 2);
if (offset != StringRef::npos && (offset == MArch.size() || MArch[offset] == 'v'))
MArch = MArch.substr(offset);
if (MArch == "") { const char *CPU = ARMTargetParser::getDefaultCPU(MArch);
// If no specific architecture version is requested, return the minimum CPU if (CPU)
// required by the OS and environment. return CPU;
switch (getOS()) {
case llvm::Triple::NetBSD: // If no specific architecture version is requested, return the minimum CPU
switch (getEnvironment()) { // required by the OS and environment.
case llvm::Triple::GNUEABIHF: switch (getOS()) {
case llvm::Triple::GNUEABI: case llvm::Triple::NetBSD:
case llvm::Triple::EABIHF: switch (getEnvironment()) {
case llvm::Triple::EABI: case llvm::Triple::GNUEABIHF:
return "arm926ej-s"; case llvm::Triple::GNUEABI:
default: case llvm::Triple::EABIHF:
return "strongarm"; case llvm::Triple::EABI:
} return "arm926ej-s";
case llvm::Triple::NaCl:
return "cortex-a8";
default: default:
switch (getEnvironment()) { return "strongarm";
case llvm::Triple::EABIHF: }
case llvm::Triple::GNUEABIHF: case llvm::Triple::NaCl:
return "arm1176jzf-s"; return "cortex-a8";
default: default:
return "arm7tdmi"; switch (getEnvironment()) {
} case llvm::Triple::EABIHF:
case llvm::Triple::GNUEABIHF:
return "arm1176jzf-s";
default:
return "arm7tdmi";
} }
} else {
result = llvm::StringSwitch<const char *>(MArch)
.Cases("v2", "v2a", "arm2")
.Case("v3", "arm6")
.Case("v3m", "arm7m")
.Case("v4", "strongarm")
.Case("v4t", "arm7tdmi")
.Cases("v5", "v5t", "arm10tdmi")
.Cases("v5e", "v5te", "arm1022e")
.Case("v5tej", "arm926ej-s")
.Case("v6", "arm1136jf-s")
.Case("v6j", "arm1136j-s")
.Cases("v6k", "v6z", "v6zk", "arm1176jzf-s")
.Case("v6t2", "arm1156t2-s")
.Cases("v6m", "v6-m", "v6sm", "v6s-m", "cortex-m0")
.Cases("v7", "v7a", "v7-a", "v7l", "v7-l", "cortex-a8")
.Cases("v7s", "v7-s", "swift")
.Cases("v7r", "v7-r", "cortex-r4")
.Cases("v7m", "v7-m", "cortex-m3")
.Cases("v7em", "v7e-m", "cortex-m4")
.Cases("v8", "v8a", "v8-a", "cortex-a53")
.Cases("v8.1a", "v8.1-a", "generic")
.Case("ep9312", "ep9312")
.Case("iwmmxt", "iwmmxt")
.Case("xscale", "xscale")
.Default(nullptr);
} }
return result; llvm_unreachable("invalid arch name");
} }

157
unittests/ADT/TripleTest.cpp
View File

@ -688,35 +688,145 @@ TEST(TripleTest, NormalizeWindows) {
} }
TEST(TripleTest, getARMCPUForArch) { TEST(TripleTest, getARMCPUForArch) {
// Standard ARM Architectures.
{
llvm::Triple Triple("armv4-unknown-eabi");
EXPECT_STREQ("strongarm", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv4t-unknown-eabi");
EXPECT_STREQ("arm7tdmi", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv5-unknown-eabi");
EXPECT_STREQ("arm10tdmi", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv5t-unknown-eabi");
EXPECT_STREQ("arm10tdmi", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv5e-unknown-eabi");
EXPECT_STREQ("arm1022e", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv5tej-unknown-eabi");
EXPECT_STREQ("arm926ej-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6-unknown-eabi");
EXPECT_STREQ("arm1136jf-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6j-unknown-eabi");
EXPECT_STREQ("arm1136j-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6k-unknown-eabi");
EXPECT_STREQ("arm1176jzf-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6zk-unknown-eabi");
EXPECT_STREQ("arm1176jzf-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6t2-unknown-eabi");
EXPECT_STREQ("arm1156t2-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6m-unknown-eabi");
EXPECT_STREQ("cortex-m0", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7-unknown-eabi");
EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7a-unknown-eabi");
EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7m-unknown-eabi");
EXPECT_STREQ("cortex-m3", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7r-unknown-eabi");
EXPECT_STREQ("cortex-r4", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7r-unknown-eabi");
EXPECT_STREQ("cortex-r4", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7r-unknown-eabi");
EXPECT_STREQ("cortex-r4", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7r-unknown-eabi");
EXPECT_STREQ("cortex-r4", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv8a-unknown-eabi");
EXPECT_STREQ("cortex-a53", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv8.1a-unknown-eabi");
EXPECT_STREQ("generic", Triple.getARMCPUForArch());
}
// Non-synonym names, using -march style, not default arch.
{
llvm::Triple Triple("arm");
EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch("armv7-a"));
}
{
llvm::Triple Triple("arm");
EXPECT_STREQ("cortex-m3", Triple.getARMCPUForArch("armv7-m"));
}
{
llvm::Triple Triple("arm");
EXPECT_STREQ("cortex-a53", Triple.getARMCPUForArch("armv8"));
}
{
llvm::Triple Triple("arm");
EXPECT_STREQ("cortex-a53", Triple.getARMCPUForArch("armv8-a"));
}
// Platform specific defaults.
{
llvm::Triple Triple("arm--nacl");
EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch());
}
{ {
llvm::Triple Triple("armv6-unknown-freebsd"); llvm::Triple Triple("armv6-unknown-freebsd");
EXPECT_STREQ("arm1176jzf-s", Triple.getARMCPUForArch()); EXPECT_STREQ("arm1176jzf-s", Triple.getARMCPUForArch());
} }
{
llvm::Triple Triple("arm--win32");
EXPECT_STREQ("cortex-a9", Triple.getARMCPUForArch());
}
// Some alternative architectures
{
llvm::Triple Triple("xscale-unknown-eabi");
EXPECT_STREQ("xscale", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("iwmmxt-unknown-eabi");
EXPECT_STREQ("iwmmxt", Triple.getARMCPUForArch());
}
{ {
llvm::Triple Triple("armv7s-apple-ios7"); llvm::Triple Triple("armv7s-apple-ios7");
EXPECT_STREQ("swift", Triple.getARMCPUForArch()); EXPECT_STREQ("swift", Triple.getARMCPUForArch());
} }
{ {
llvm::Triple Triple("armv7-apple-ios7"); llvm::Triple Triple("armv7em-apple-ios7");
EXPECT_STREQ("cortex-m4", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv7l-linux-gnueabihf");
EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch()); EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch());
EXPECT_STREQ("swift", Triple.getARMCPUForArch("armv7s"));
} }
{ {
llvm::Triple Triple("arm--nacl"); llvm::Triple Triple("armv6sm-apple-ios7");
EXPECT_STREQ("cortex-a8", Triple.getARMCPUForArch("arm")); EXPECT_STREQ("cortex-m0", Triple.getARMCPUForArch());
}
// armebv6 and armv6eb are permitted, but armebv6eb is not
{
llvm::Triple Triple("armebv6-non-eabi");
EXPECT_STREQ("arm1136jf-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6eb-none-eabi");
EXPECT_STREQ("arm1136jf-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armebv6eb-none-eabi");
EXPECT_EQ(nullptr, Triple.getARMCPUForArch());
} }
// armeb is permitted, but armebeb is not // armeb is permitted, but armebeb is not
{ {
@ -727,6 +837,19 @@ TEST(TripleTest, getARMCPUForArch) {
llvm::Triple Triple("armebeb-none-eabi"); llvm::Triple Triple("armebeb-none-eabi");
EXPECT_EQ(nullptr, Triple.getARMCPUForArch()); EXPECT_EQ(nullptr, Triple.getARMCPUForArch());
} }
{
llvm::Triple Triple("armebv6eb-none-eabi");
EXPECT_EQ(nullptr, Triple.getARMCPUForArch());
}
// armebv6 and armv6eb are permitted, but armebv6eb is not
{
llvm::Triple Triple("armebv6-non-eabi");
EXPECT_STREQ("arm1136jf-s", Triple.getARMCPUForArch());
}
{
llvm::Triple Triple("armv6eb-none-eabi");
EXPECT_STREQ("arm1136jf-s", Triple.getARMCPUForArch());
}
// xscaleeb is permitted, but armebxscale is not // xscaleeb is permitted, but armebxscale is not
{ {
llvm::Triple Triple("xscaleeb-none-eabi"); llvm::Triple Triple("xscaleeb-none-eabi");