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- Identify a vector_shuffle that can be turned into an undef, e.g.
shuffle V1, <undef>, <undef, undef, 4, 5> - Fix some suspicious logic into LowerVectorShuffle that cause less than optimal code by failing to identify MOVL (move to lowest element of a vector). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30171 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1719,7 +1719,8 @@ bool X86::isMOVLMask(SDNode *N) {
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/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
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/// of what x86 movss want. X86 movs requires the lowest element to be lowest
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/// element of vector 2 and the other elements to come from vector 1 in order.
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static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false) {
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static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false,
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bool V2IsUndef = false) {
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unsigned NumElems = Ops.size();
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if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
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return false;
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@ -1729,22 +1730,20 @@ static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false)
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for (unsigned i = 1; i < NumElems; ++i) {
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SDOperand Arg = Ops[i];
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if (V2IsSplat) {
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if (!isUndefOrEqual(Arg, NumElems))
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return false;
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} else {
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if (!isUndefOrEqual(Arg, i+NumElems))
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return false;
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}
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if (!(isUndefOrEqual(Arg, i+NumElems) ||
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(V2IsUndef && isUndefOrInRange(Arg, NumElems, NumElems*2)) ||
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(V2IsSplat && isUndefOrEqual(Arg, NumElems))))
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return false;
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}
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return true;
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}
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static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false) {
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static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
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bool V2IsUndef = false) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
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return isCommutedMOVL(Ops, V2IsSplat);
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return isCommutedMOVL(Ops, V2IsSplat, V2IsUndef);
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}
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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@ -2034,6 +2033,29 @@ static bool isSplatVector(SDNode *N) {
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return true;
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}
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/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
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/// to an undef.
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static bool isUndefShuffle(SDNode *N) {
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if (N->getOpcode() != ISD::BUILD_VECTOR)
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return false;
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SDOperand V1 = N->getOperand(0);
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SDOperand V2 = N->getOperand(1);
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SDOperand Mask = N->getOperand(2);
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unsigned NumElems = Mask.getNumOperands();
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for (unsigned i = 0; i != NumElems; ++i) {
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SDOperand Arg = Mask.getOperand(i);
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if (Arg.getOpcode() != ISD::UNDEF) {
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
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return false;
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else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
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return false;
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}
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}
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return true;
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}
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/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
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/// that point to V2 points to its first element.
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static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
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@ -2402,6 +2424,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
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bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
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if (isUndefShuffle(Op.Val))
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return DAG.getNode(ISD::UNDEF, VT);
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if (isSplatMask(PermMask.Val)) {
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if (NumElems <= 4) return Op;
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// Promote it to a v4i32 splat.
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@ -2422,17 +2447,18 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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ShouldXformToMOVLP(V1.Val, PermMask.Val))
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return CommuteVectorShuffle(Op, DAG);
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bool V1IsSplat = isSplatVector(V1.Val) || V1.getOpcode() == ISD::UNDEF;
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bool V2IsSplat = isSplatVector(V2.Val) || V2.getOpcode() == ISD::UNDEF;
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if (V1IsSplat && !V2IsSplat) {
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bool V1IsSplat = isSplatVector(V1.Val);
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bool V2IsSplat = isSplatVector(V2.Val);
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if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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V2IsSplat = true;
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std::swap(V1IsSplat, V2IsSplat);
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std::swap(V1IsUndef, V2IsUndef);
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}
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if (isCommutedMOVL(PermMask.Val, V2IsSplat)) {
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if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
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if (V2IsUndef) return V1;
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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