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[InstCombine][SSE] Regenerate MOVSX/MOVZX tests

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268201 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2016-05-01 18:28:45 +00:00
parent fc16410133
commit 8d33576d14
2 changed files with 116 additions and 114 deletions
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115
test/Transforms/InstCombine/x86-pmovsx.ll
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@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
@ -19,118 +20,118 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16>) nounwind readnone
;
define <4 x i32> @sse41_pmovsxbd(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovsxbd
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: sext <4 x i8> %1 to <4 x i32>
; CHECK-NEXT: ret <4 x i32> %2
; CHECK-LABEL: @sse41_pmovsxbd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %v)
ret <4 x i32> %res
}
define <2 x i64> @sse41_pmovsxbq(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovsxbq
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: sext <2 x i8> %1 to <2 x i64>
; CHECK-NEXT: ret <2 x i64> %2
; CHECK-LABEL: @sse41_pmovsxbq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
;
%res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %v)
ret <2 x i64> %res
}
define <8 x i16> @sse41_pmovsxbw(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovsxbw
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: sext <8 x i8> %1 to <8 x i16>
; CHECK-NEXT: ret <8 x i16> %2
; CHECK-LABEL: @sse41_pmovsxbw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i16>
; CHECK-NEXT: ret <8 x i16> [[TMP2]]
;
%res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %v)
ret <8 x i16> %res
}
define <2 x i64> @sse41_pmovsxdq(<4 x i32> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovsxdq
; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: sext <2 x i32> %1 to <2 x i64>
; CHECK-NEXT: ret <2 x i64> %2
; CHECK-LABEL: @sse41_pmovsxdq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
;
%res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %v)
ret <2 x i64> %res
}
define <4 x i32> @sse41_pmovsxwd(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovsxwd
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: sext <4 x i16> %1 to <4 x i32>
; CHECK-NEXT: ret <4 x i32> %2
; CHECK-LABEL: @sse41_pmovsxwd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %v)
ret <4 x i32> %res
}
define <2 x i64> @sse41_pmovsxwq(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovsxwq
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: sext <2 x i16> %1 to <2 x i64>
; CHECK-NEXT: ret <2 x i64> %2
; CHECK-LABEL: @sse41_pmovsxwq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
;
%res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %v)
ret <2 x i64> %res
}
define <8 x i32> @avx2_pmovsxbd(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovsxbd
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: sext <8 x i8> %1 to <8 x i32>
; CHECK-NEXT: ret <8 x i32> %2
; CHECK-LABEL: @avx2_pmovsxbd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i32>
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
;
%res = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %v)
ret <8 x i32> %res
}
define <4 x i64> @avx2_pmovsxbq(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovsxbq
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: sext <4 x i8> %1 to <4 x i64>
; CHECK-NEXT: ret <4 x i64> %2
; CHECK-LABEL: @avx2_pmovsxbq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i64>
; CHECK-NEXT: ret <4 x i64> [[TMP2]]
;
%res = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %v)
ret <4 x i64> %res
}
define <16 x i16> @avx2_pmovsxbw(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovsxbw
; CHECK-NEXT: sext <16 x i8> %v to <16 x i16>
; CHECK-NEXT: ret <16 x i16> %1
; CHECK-LABEL: @avx2_pmovsxbw(
; CHECK-NEXT: [[TMP1:%.*]] = sext <16 x i8> %v to <16 x i16>
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
;
%res = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %v)
ret <16 x i16> %res
}
define <4 x i64> @avx2_pmovsxdq(<4 x i32> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovsxdq
; CHECK-NEXT: sext <4 x i32> %v to <4 x i64>
; CHECK-NEXT: ret <4 x i64> %1
; CHECK-LABEL: @avx2_pmovsxdq(
; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i32> %v to <4 x i64>
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%res = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %v)
ret <4 x i64> %res
}
define <8 x i32> @avx2_pmovsxwd(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovsxwd
; CHECK-NEXT: sext <8 x i16> %v to <8 x i32>
; CHECK-NEXT: ret <8 x i32> %1
; CHECK-LABEL: @avx2_pmovsxwd(
; CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i16> %v to <8 x i32>
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
;
%res = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %v)
ret <8 x i32> %res
}
define <4 x i64> @avx2_pmovsxwq(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovsxwq
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: sext <4 x i16> %1 to <4 x i64>
; CHECK-NEXT: ret <4 x i64> %2
; CHECK-LABEL: @avx2_pmovsxwq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i64>
; CHECK-NEXT: ret <4 x i64> [[TMP2]]
;
%res = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %v)
ret <4 x i64> %res
}

115
test/Transforms/InstCombine/x86-pmovzx.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone
@ -19,118 +20,118 @@ declare <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16>) nounwind readnone
;
define <4 x i32> @sse41_pmovzxbd(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovzxbd
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: zext <4 x i8> %1 to <4 x i32>
; CHECK-NEXT: ret <4 x i32> %2
; CHECK-LABEL: @sse41_pmovzxbd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %v)
ret <4 x i32> %res
}
define <2 x i64> @sse41_pmovzxbq(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovzxbq
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: zext <2 x i8> %1 to <2 x i64>
; CHECK-NEXT: ret <2 x i64> %2
; CHECK-LABEL: @sse41_pmovzxbq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
;
%res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %v)
ret <2 x i64> %res
}
define <8 x i16> @sse41_pmovzxbw(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovzxbw
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: zext <8 x i8> %1 to <8 x i16>
; CHECK-NEXT: ret <8 x i16> %2
; CHECK-LABEL: @sse41_pmovzxbw(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i16>
; CHECK-NEXT: ret <8 x i16> [[TMP2]]
;
%res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %v)
ret <8 x i16> %res
}
define <2 x i64> @sse41_pmovzxdq(<4 x i32> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovzxdq
; CHECK-NEXT: shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: zext <2 x i32> %1 to <2 x i64>
; CHECK-NEXT: ret <2 x i64> %2
; CHECK-LABEL: @sse41_pmovzxdq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
;
%res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %v)
ret <2 x i64> %res
}
define <4 x i32> @sse41_pmovzxwd(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovzxwd
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: zext <4 x i16> %1 to <4 x i32>
; CHECK-NEXT: ret <4 x i32> %2
; CHECK-LABEL: @sse41_pmovzxwd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %v)
ret <4 x i32> %res
}
define <2 x i64> @sse41_pmovzxwq(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @sse41_pmovzxwq
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: zext <2 x i16> %1 to <2 x i64>
; CHECK-NEXT: ret <2 x i64> %2
; CHECK-LABEL: @sse41_pmovzxwq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
;
%res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %v)
ret <2 x i64> %res
}
define <8 x i32> @avx2_pmovzxbd(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovzxbd
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: zext <8 x i8> %1 to <8 x i32>
; CHECK-NEXT: ret <8 x i32> %2
; CHECK-LABEL: @avx2_pmovzxbd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i32>
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
;
%res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %v)
ret <8 x i32> %res
}
define <4 x i64> @avx2_pmovzxbq(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovzxbq
; CHECK-NEXT: shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: zext <4 x i8> %1 to <4 x i64>
; CHECK-NEXT: ret <4 x i64> %2
; CHECK-LABEL: @avx2_pmovzxbq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i64>
; CHECK-NEXT: ret <4 x i64> [[TMP2]]
;
%res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %v)
ret <4 x i64> %res
}
define <16 x i16> @avx2_pmovzxbw(<16 x i8> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovzxbw
; CHECK-NEXT: zext <16 x i8> %v to <16 x i16>
; CHECK-NEXT: ret <16 x i16> %1
; CHECK-LABEL: @avx2_pmovzxbw(
; CHECK-NEXT: [[TMP1:%.*]] = zext <16 x i8> %v to <16 x i16>
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
;
%res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %v)
ret <16 x i16> %res
}
define <4 x i64> @avx2_pmovzxdq(<4 x i32> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovzxdq
; CHECK-NEXT: zext <4 x i32> %v to <4 x i64>
; CHECK-NEXT: ret <4 x i64> %1
; CHECK-LABEL: @avx2_pmovzxdq(
; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i32> %v to <4 x i64>
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
;
%res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %v)
ret <4 x i64> %res
}
define <8 x i32> @avx2_pmovzxwd(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovzxwd
; CHECK-NEXT: zext <8 x i16> %v to <8 x i32>
; CHECK-NEXT: ret <8 x i32> %1
; CHECK-LABEL: @avx2_pmovzxwd(
; CHECK-NEXT: [[TMP1:%.*]] = zext <8 x i16> %v to <8 x i32>
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
;
%res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %v)
ret <8 x i32> %res
}
define <4 x i64> @avx2_pmovzxwq(<8 x i16> %v) nounwind readnone {
; CHECK-LABEL: @avx2_pmovzxwq
; CHECK-NEXT: shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: zext <4 x i16> %1 to <4 x i64>
; CHECK-NEXT: ret <4 x i64> %2
; CHECK-LABEL: @avx2_pmovzxwq(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i64>
; CHECK-NEXT: ret <4 x i64> [[TMP2]]
;
%res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %v)
ret <4 x i64> %res
}