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Fix the assertion error in collectLoopUniforms caused by empty Worklist before expanding.
Contributed-by: David Callahan Differential Revision: https://reviews.llvm.org/D22886 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276943 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4859,7 +4859,7 @@ void LoopVectorizationLegality::collectLoopUniforms() {
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// out of scope. It ensures a uniform instruction will only be used
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// out of scope. It ensures a uniform instruction will only be used
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// by uniform instructions or out of scope instructions.
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// by uniform instructions or out of scope instructions.
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unsigned idx = 0;
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unsigned idx = 0;
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do {
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while (idx != Worklist.size()) {
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Instruction *I = Worklist[idx++];
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Instruction *I = Worklist[idx++];
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for (auto OV : I->operand_values()) {
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for (auto OV : I->operand_values()) {
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@ -4873,7 +4873,7 @@ void LoopVectorizationLegality::collectLoopUniforms() {
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DEBUG(dbgs() << "LV: Found uniform instruction: " << *OI << "\n");
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DEBUG(dbgs() << "LV: Found uniform instruction: " << *OI << "\n");
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}
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}
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}
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}
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} while (idx != Worklist.size());
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}
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// For an instruction to be added into Worklist above, all its users inside
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// For an instruction to be added into Worklist above, all its users inside
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// the current loop should be already added into Worklist. This condition
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// the current loop should be already added into Worklist. This condition
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19
test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
Normal file
19
test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
Normal file
@ -0,0 +1,19 @@
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; RUN: opt < %s -loop-vectorize -S
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define void @foo() local_unnamed_addr {
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entry:
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%exitcond = icmp eq i64 3, 3
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br label %for.body
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for.body: ; preds = %entry
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%i.05 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%total1 = add nsw i64 %i.05, 3
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%inc = add nuw nsw i64 %i.05, 1
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br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !0
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for.end: ; preds = %for.body
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ret void
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}
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!0 = distinct !{!0, !1}
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!1 = !{!"llvm.loop.vectorize.enable", i1 true}
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