RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-26 05:56:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Change shouldSplitVectorElementType to better match the description.

Browse Source 
Pass the entire vector type, and not just the element.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205247 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-03-31 20:54:58 +00:00
parent f2529ba127
commit 8d8c507bbf
6 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/Target/TargetLowering.h
View File

@ -183,7 +183,7 @@ public:
/// Return true if a vector of the given type should be split
/// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type
/// legalization.
virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
virtual bool shouldSplitVectorType(EVT /*VT*/) const { return false; }
// There are two general methods for expanding a BUILD_VECTOR node:
// 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle

2
lib/CodeGen/TargetLoweringBase.cpp
View File

@ -1087,7 +1087,7 @@ void TargetLoweringBase::computeRegisterProperties() {
// that wider vector type.
MVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
if (NElts != 1 && !shouldSplitVectorType(VT)) {
bool IsLegalWiderType = false;
// First try to promote the elements of integer vectors. If no legal
// promotion was found, fallback to the widen-vector method.

4
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -331,8 +331,8 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
bool NVPTXTargetLowering::shouldSplitVectorElementType(EVT VT) const {
return VT == MVT::i1;
bool NVPTXTargetLowering::shouldSplitVectorType(EVT VT) const {
return VT.getScalarType() == MVT::i1;
}
SDValue

2
lib/Target/NVPTX/NVPTXISelLowering.h
View File

@ -141,7 +141,7 @@ public:
// PTX always uses 32-bit shift amounts
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
virtual bool shouldSplitVectorElementType(EVT VT) const;
virtual bool shouldSplitVectorType(EVT VT) const override;
private:
const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here

4
lib/Target/R600/SIISelLowering.cpp
View File

@ -211,8 +211,8 @@ bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
return VT.bitsGT(MVT::i32);
}
bool SITargetLowering::shouldSplitVectorElementType(EVT VT) const {
return VT.bitsLE(MVT::i16);
bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
return VT.getScalarType().bitsLE(MVT::i16);
}
bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,

2
lib/Target/R600/SIISelLowering.h
View File

@ -50,7 +50,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
public:
SITargetLowering(TargetMachine &tm);
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, bool *IsFast) const;
virtual bool shouldSplitVectorElementType(EVT VT) const;
virtual bool shouldSplitVectorType(EVT VT) const override;
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;