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Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56118 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -875,6 +875,8 @@ void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
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}
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}
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo* TRI) {
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@ -919,6 +921,61 @@ SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg,
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return (SrcSize + DstSize) <= Threshold;
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}
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/// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
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/// register with a physical register, check if any of the virtual register
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/// operand is a sub-register use or def. If so, make sure it won't result
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/// in an illegal extract_subreg or insert_subreg instruction. e.g.
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/// vr1024 = extract_subreg vr1025, 1
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/// ...
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/// vr1024 = mov8rr AH
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/// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
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/// AH does not have a super-reg whose sub-register 1 is AH.
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bool
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SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
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unsigned VirtReg,
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unsigned PhysReg) {
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for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
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E = mri_->reg_end(); I != E; ++I) {
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MachineOperand &O = I.getOperand();
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MachineInstr *MI = &*I;
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if (MI == CopyMI || JoinedCopies.count(MI))
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continue;
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unsigned SubIdx = O.getSubReg();
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if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
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return true;
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if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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SubIdx = MI->getOperand(2).getImm();
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if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
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return true;
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if (O.isDef()) {
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unsigned SrcReg = MI->getOperand(1).getReg();
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const TargetRegisterClass *RC =
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TargetRegisterInfo::isPhysicalRegister(SrcReg)
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? tri_->getPhysicalRegisterRegClass(SrcReg)
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: mri_->getRegClass(SrcReg);
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if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
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return true;
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}
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}
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if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
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SubIdx = MI->getOperand(3).getImm();
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if (VirtReg == MI->getOperand(0).getReg()) {
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if (!tri_->getSubReg(PhysReg, SubIdx))
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return true;
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} else {
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unsigned DstReg = MI->getOperand(0).getReg();
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const TargetRegisterClass *RC =
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TargetRegisterInfo::isPhysicalRegister(DstReg)
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? tri_->getPhysicalRegisterRegClass(DstReg)
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: mri_->getRegClass(DstReg);
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if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
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return true;
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}
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}
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}
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return false;
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}
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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@ -1112,6 +1169,12 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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}
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}
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// Will it create illegal extract_subreg / insert_subreg?
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if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
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return false;
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if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
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return false;
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LiveInterval &SrcInt = li_->getInterval(SrcReg);
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LiveInterval &DstInt = li_->getInterval(DstReg);
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assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
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@ -223,6 +223,13 @@ namespace llvm {
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bool isProfitableToCoalesceToSubRC(unsigned SrcReg, unsigned DstReg,
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MachineBasicBlock *MBB);
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/// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
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/// register with a physical register, check if any of the virtual register
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/// operand is a sub-register use or def. If so, make sure it won't result
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/// in an illegal extract_subreg or insert_subreg instruction.
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bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
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unsigned VirtReg, unsigned PhysReg);
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/// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
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/// the specified live interval is defined by a copy from the specified
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/// register.
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33
test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
Normal file
33
test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
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@ -0,0 +1,33 @@
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; RUN: llvm-as < %s | llc -march=x86
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; PR2748
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@g_73 = external global i32 ; <i32*> [#uses=1]
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@g_5 = external global i32 ; <i32*> [#uses=1]
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define i32 @func_44(i16 signext %p_46) nounwind {
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entry:
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%0 = load i32* @g_5, align 4 ; <i32> [#uses=1]
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%1 = ashr i32 %0, 1 ; <i32> [#uses=1]
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%2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]
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%3 = zext i1 %2 to i32 ; <i32> [#uses=1]
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%4 = load i32* @g_73, align 4 ; <i32> [#uses=1]
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%5 = zext i16 %p_46 to i64 ; <i64> [#uses=1]
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%6 = sub i64 0, %5 ; <i64> [#uses=1]
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%7 = trunc i64 %6 to i8 ; <i8> [#uses=2]
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%8 = trunc i32 %4 to i8 ; <i8> [#uses=2]
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%9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
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br i1 %9, label %bb11, label %bb12
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bb11: ; preds = %entry
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%10 = urem i8 %7, %8 ; <i8> [#uses=1]
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br label %bb12
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bb12: ; preds = %bb11, %entry
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%.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ] ; <i8> [#uses=1]
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%11 = icmp ne i8 %.014.in, 0 ; <i1> [#uses=1]
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%12 = zext i1 %11 to i32 ; <i32> [#uses=1]
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%13 = tail call i32 (...)* @func_48( i32 %12, i32 %3, i32 0 ) nounwind ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @func_48(...)
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