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claim ST(x) registers are 80 bits, which is true. This doesn't affect

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codegen yet because these can't be spilled (they don't exist until after RA).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-03-09 07:49:01 +00:00
parent d43d85ccc9
commit 8dc023f684
1 changed files with 1 additions and 1 deletions
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2
lib/Target/X86/X86RegisterInfo.td
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@ -488,7 +488,7 @@ def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>
// Floating point stack registers (these are not allocatable by the
// register allocator - the floating point stackifier is responsible
// for transforming FPn allocations to STn registers)
def RST : RegisterClass<"X86", [f64], 32,
def RST : RegisterClass<"X86", [f80], 32,
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;