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[Hexagon] Bring HexagonInstrInfo up to date
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253986 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
42fec0866c
commit
8e716832ef
@ -71,6 +71,7 @@ class NewValueRel: PredNewRel;
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// NewValueRel - Filter class used to relate load/store instructions having
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// different addressing modes with each other.
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class AddrModeRel: NewValueRel;
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class IntrinsicsRel;
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate non-predicate instructions with their
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@ -186,6 +187,37 @@ def getRegForm : InstrMapping {
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let ValueCols = [["reg"]];
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}
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def getRegShlForm : InstrMapping {
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let FilterClass = "ImmRegShl";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["InputType"];
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let KeyCol = ["imm"];
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let ValueCols = [["reg"]];
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}
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def notTakenBranchPrediction : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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let ColFields = ["isBrTaken"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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def takenBranchPrediction : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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let ColFields = ["isBrTaken"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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def getRealHWInstr : InstrMapping {
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let FilterClass = "IntrinsicsRel";
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let RowFields = ["BaseOpcode"];
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let ColFields = ["InstrType"];
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let KeyCol = ["Pseudo"];
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let ValueCols = [["Pseudo"], ["Real"]];
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}
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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@ -210,6 +242,10 @@ def : Proc<"hexagonv4", HexagonModelV4,
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[ArchV4]>;
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def : Proc<"hexagonv5", HexagonModelV4,
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[ArchV4, ArchV5]>;
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def : Proc<"hexagonv55", HexagonModelV55,
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[ArchV4, ArchV5, ArchV55]>;
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def : Proc<"hexagonv60", HexagonModelV60,
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[ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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File diff suppressed because it is too large
Load Diff
@ -1,4 +1,3 @@
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//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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@ -28,23 +27,18 @@ namespace llvm {
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struct EVT;
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class HexagonSubtarget;
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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virtual void anchor();
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const HexagonRegisterInfo RI;
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const HexagonSubtarget &Subtarget;
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public:
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typedef unsigned Opcode_t;
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explicit HexagonInstrInfo(HexagonSubtarget &ST);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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/// TargetInstrInfo overrides.
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///
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const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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@ -52,7 +46,7 @@ public:
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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@ -60,50 +54,118 @@ public:
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with a conditional branch and it falls through to a
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/// successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These operands can be
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/// passed to other TargetInstrInfo methods to create new branches.
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/// 4. If this block ends with a conditional branch followed by an
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/// unconditional branch, it returns the 'true' destination in TBB, the
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/// 'false' destination in FBB, and a list of operands that evaluate the
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/// condition. These operands can be passed to other TargetInstrInfo
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/// methods to create new branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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/// If AllowModify is true, then this routine is allowed to modify the basic
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/// block (e.g. delete instructions after the unconditional branch).
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///
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bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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/// Remove the branching code at the end of the specific MBB.
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/// This is only invoked in cases where AnalyzeBranch returns success. It
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/// returns the number of instructions that were removed.
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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/// Insert branch code into the end of the specified MachineBasicBlock.
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/// The operands to this method are the same as those
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/// returned by AnalyzeBranch. This is only invoked in cases where
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/// AnalyzeBranch returns success. It returns the number of instructions
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/// inserted.
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///
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/// It is also invoked by tail merging to add unconditional branches in
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/// cases where AnalyzeBranch doesn't apply because there was no original
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/// branch to analyze. At least this much must be implemented, else tail
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/// merging needs to be disabled.
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const override;
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/// Return true if it's profitable to predicate
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/// instructions with accumulated instruction latency of "NumCycles"
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/// of the specified basic block, where the probability of the instructions
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/// being executed is given by Probability, and Confidence is a measure
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/// of our confidence that it will be properly predicted.
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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BranchProbability Probability) const override;
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/// Second variant of isProfitableToIfCvt. This one
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/// checks for the case where two basic blocks from true and false path
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/// of a if-then-else (diamond) are predicated on mutally exclusive
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/// predicates, where the probability of the true path being taken is given
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/// by Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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BranchProbability Probability) const override;
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/// Return true if it's profitable for if-converter to duplicate instructions
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/// of specified accumulated instruction latencies in the specified MBB to
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/// enable if-conversion.
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/// The probability of the instructions being executed is given by
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/// Probability, and Confidence is a measure of our confidence that it
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/// will be properly predicted.
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override;
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/// Emit instructions to copy a pair of physical registers.
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///
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/// This function should support copies within any legal register class as
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/// well as any cross-class copies created during instruction selection.
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///
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/// The source and destination registers may overlap, which may require a
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/// careful implementation when multiple copy instructions are required for
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/// large registers. See for example the ARM target.
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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/// Store the specified register of the given register class to the specified
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/// stack frame index. The store instruction is to be added to the given
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/// machine basic block before the specified machine instruction. If isKill
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/// is true, the register operand is the last use and must be marked kill.
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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/// Load the specified register of the given register class from the specified
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/// stack frame index. The load instruction is to be added to the given
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/// machine basic block before the specified machine instruction.
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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/// expandPostRAPseudo - This function is called for all pseudo instructions
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/// This function is called for all pseudo instructions
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/// that remain after register allocation. Many pseudo instructions are
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/// created to help register allocation. This is the place to convert them
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/// into real instructions. The target can edit MI in place, or it can insert
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@ -111,122 +173,223 @@ public:
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/// anything was changed.
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt,
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int FrameIndex) const override;
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/// Reverses the branch condition of the specified condition list,
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/// returning false on success and true if it cannot be reversed.
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const override;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt,
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MachineInstr *LoadMI) const override {
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return nullptr;
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}
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/// Insert a noop into the instruction stream at the specified point.
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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unsigned createVR(MachineFunction* MF, MVT VT) const;
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/// Returns true if the instruction is already predicated.
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bool isPredicated(const MachineInstr *MI) const override;
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bool isBranch(const MachineInstr *MI) const;
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bool isPredicable(MachineInstr *MI) const override;
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/// Convert the instruction into a predicated instruction.
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/// It returns true if the operation was successful.
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bool PredicateInstruction(MachineInstr *MI,
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ArrayRef<MachineOperand> Cond) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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BranchProbability Probability) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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BranchProbability Probability) const override;
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bool isPredicated(const MachineInstr *MI) const override;
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bool isPredicated(unsigned Opcode) const;
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bool isPredicatedTrue(const MachineInstr *MI) const;
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bool isPredicatedTrue(unsigned Opcode) const;
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bool isPredicatedNew(const MachineInstr *MI) const;
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bool isPredicatedNew(unsigned Opcode) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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/// Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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/// If the specified instruction defines any predicate
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/// or condition code register(s) used for predication, returns true as well
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/// as the definition predicate(s) by reference.
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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BranchProbability Probability) const override;
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DFAPacketizer *
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CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
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/// Return true if the specified instruction can be predicated.
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/// By default, this returns true for every instruction with a
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/// PredicateOperand.
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bool isPredicable(MachineInstr *MI) const override;
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/// Test if the given instruction should be considered a scheduling boundary.
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/// This primarily includes labels and terminators.
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bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
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bool isValidAutoIncImm(const EVT VT, const int Offset) const;
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bool isMemOp(const MachineInstr *MI) const;
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bool isSpillPredRegOp(const MachineInstr *MI) const;
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bool isU6_3Immediate(const int value) const;
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bool isU6_2Immediate(const int value) const;
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bool isU6_1Immediate(const int value) const;
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bool isU6_0Immediate(const int value) const;
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bool isS4_3Immediate(const int value) const;
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bool isS4_2Immediate(const int value) const;
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bool isS4_1Immediate(const int value) const;
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bool isS4_0Immediate(const int value) const;
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bool isS12_Immediate(const int value) const;
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bool isU6_Immediate(const int value) const;
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bool isS8_Immediate(const int value) const;
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bool isS6_Immediate(const int value) const;
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bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
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bool isConditionalTransfer(const MachineInstr* MI) const;
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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unsigned getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const override;
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/// Allocate and return a hazard recognizer to use for this target when
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/// scheduling the machine instructions after register allocation.
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ScheduleHazardRecognizer*
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
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const ScheduleDAG *DAG) const override;
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/// For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const override;
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/// Compute the instruction latency of a given instruction.
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/// If the instruction has higher cost when predicated, it's returned via
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/// PredCost.
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const override;
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/// Create machine specific model for scheduling.
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DFAPacketizer *
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CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
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// Sometimes, it is possible for the target
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// to tell, even without aliasing information, that two MIs access different
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// memory addresses. This function returns true if two MIs access different
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// memory addresses and false otherwise.
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bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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AliasAnalysis *AA = nullptr)
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const override;
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/// HexagonInstrInfo specifics.
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///
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const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
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unsigned createVR(MachineFunction* MF, MVT VT) const;
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bool isAbsoluteSet(const MachineInstr* MI) const;
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bool isAccumulator(const MachineInstr *MI) const;
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bool isComplex(const MachineInstr *MI) const;
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bool isCompoundBranchInstr(const MachineInstr *MI) const;
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bool isCondInst(const MachineInstr *MI) const;
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bool isConditionalALU32 (const MachineInstr* MI) const;
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bool isConditionalLoad (const MachineInstr* MI) const;
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bool isConditionalLoad(const MachineInstr* MI) const;
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bool isConditionalStore(const MachineInstr* MI) const;
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bool isNewValueInst(const MachineInstr* MI) const;
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bool isNewValue(const MachineInstr* MI) const;
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bool isNewValue(Opcode_t Opcode) const;
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bool isDotNewInst(const MachineInstr* MI) const;
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int GetDotOldOp(const int opc) const;
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int GetDotNewOp(const MachineInstr* MI) const;
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int GetDotNewPredOp(MachineInstr *MI,
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const MachineBranchProbabilityInfo
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*MBPI) const;
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bool mayBeNewStore(const MachineInstr* MI) const;
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bool isConditionalTransfer(const MachineInstr* MI) const;
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bool isConstExtended(const MachineInstr *MI) const;
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bool isDeallocRet(const MachineInstr *MI) const;
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unsigned getInvertedPredicatedOpcode(const int Opc) const;
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bool isDependent(const MachineInstr *ProdMI,
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const MachineInstr *ConsMI) const;
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bool isDotCurInst(const MachineInstr* MI) const;
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bool isDotNewInst(const MachineInstr* MI) const;
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bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
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bool isEarlySourceInstr(MachineInstr *MI) const;
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bool isEndLoopN(unsigned Opcode) const;
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bool isExpr(unsigned OpType) const;
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bool isExtendable(const MachineInstr* MI) const;
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bool isExtended(const MachineInstr* MI) const;
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bool isPostIncrement(const MachineInstr* MI) const;
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bool isFloat(MachineInstr *MI) const;
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bool isIndirectCall(const MachineInstr *MI) const;
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bool isIndirectL4Return(const MachineInstr *MI) const;
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bool isJumpR(const MachineInstr *MI) const;
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bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
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bool isLateInstrFeedsEarlyInstr(MachineInstr *LRMI, MachineInstr *ESMI) const;
|
||||
bool isLateResultInstr(MachineInstr *MI) const;
|
||||
bool isLateSourceInstr(const MachineInstr *MI) const;
|
||||
bool isLoopN(unsigned Opcode) const;
|
||||
bool isMemOp(const MachineInstr *MI) const;
|
||||
bool isNewValue(const MachineInstr* MI) const;
|
||||
bool isNewValue(unsigned Opcode) const;
|
||||
bool isNewValueInst(const MachineInstr* MI) const;
|
||||
bool isNewValueJump(const MachineInstr* MI) const;
|
||||
bool isNewValueJump(unsigned Opcode) const;
|
||||
bool isNewValueStore(const MachineInstr* MI) const;
|
||||
bool isNewValueStore(unsigned Opcode) const;
|
||||
bool isNewValueJump(const MachineInstr* MI) const;
|
||||
bool isNewValueJump(Opcode_t Opcode) const;
|
||||
bool isNewValueJumpCandidate(const MachineInstr *MI) const;
|
||||
bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
|
||||
bool isPostIncrement(const MachineInstr* MI) const;
|
||||
bool isPredicatedNew(const MachineInstr *MI) const;
|
||||
bool isPredicatedNew(unsigned Opcode) const;
|
||||
bool isPredicatedTrue(const MachineInstr *MI) const;
|
||||
bool isPredicatedTrue(unsigned Opcode) const;
|
||||
bool isPredicated(unsigned Opcode) const;
|
||||
bool isPredicateLate(unsigned Opcode) const;
|
||||
bool isPredictedTaken(unsigned Opcode) const;
|
||||
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
|
||||
bool isSolo(const MachineInstr* MI) const;
|
||||
bool isSpillPredRegOp(const MachineInstr *MI) const;
|
||||
bool isTC1(const MachineInstr *MI) const;
|
||||
bool isTC2(const MachineInstr *MI) const;
|
||||
bool isTC2Early(const MachineInstr *MI) const;
|
||||
bool isTC4x(const MachineInstr *MI) const;
|
||||
bool isV60VectorInstruction(const MachineInstr *MI) const;
|
||||
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
|
||||
bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
|
||||
bool isVecAcc(const MachineInstr *MI) const;
|
||||
bool isVecALU(const MachineInstr *MI) const;
|
||||
bool isVecUsableNextPacket(const MachineInstr *ProdMI,
|
||||
const MachineInstr *ConsMI) const;
|
||||
|
||||
|
||||
bool hasEHLabel(const MachineBasicBlock *B) const;
|
||||
bool hasNonExtEquivalent(const MachineInstr *MI) const;
|
||||
bool hasPseudoInstrPair(MachineInstr *MI) const;
|
||||
bool hasUncondBranch(const MachineBasicBlock *B) const;
|
||||
bool mayBeCurLoad(const MachineInstr* MI) const;
|
||||
bool mayBeNewStore(const MachineInstr* MI) const;
|
||||
bool producesStall(const MachineInstr *ProdMI,
|
||||
const MachineInstr *ConsMI) const;
|
||||
bool producesStall(const MachineInstr *MI,
|
||||
MachineBasicBlock::const_instr_iterator MII) const;
|
||||
bool predCanBeUsedAsDotNew(MachineInstr *MI, unsigned PredReg) const;
|
||||
bool PredOpcodeHasJMP_c(unsigned Opcode) const;
|
||||
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
|
||||
|
||||
|
||||
unsigned getAddrMode(const MachineInstr* MI) const;
|
||||
unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
|
||||
unsigned &AccessSize) const;
|
||||
bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
|
||||
unsigned &OffsetPos) const;
|
||||
SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
|
||||
unsigned getCExtOpNum(const MachineInstr *MI) const;
|
||||
HexagonII::CompoundGroup
|
||||
getCompoundCandidateGroup(const MachineInstr *MI) const;
|
||||
unsigned getCompoundOpcode(const MachineInstr *GA,
|
||||
const MachineInstr *GB) const;
|
||||
int getCondOpcode(int Opc, bool sense) const;
|
||||
int getDotCurOp(const MachineInstr* MI) const;
|
||||
int getDotNewOp(const MachineInstr* MI) const;
|
||||
int getDotNewPredJumpOp(MachineInstr *MI,
|
||||
const MachineBranchProbabilityInfo *MBPI) const;
|
||||
int getDotNewPredOp(MachineInstr *MI,
|
||||
const MachineBranchProbabilityInfo *MBPI) const;
|
||||
int getDotOldOp(const int opc) const;
|
||||
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
|
||||
const;
|
||||
short getEquivalentHWInstr(MachineInstr *MI) const;
|
||||
MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
|
||||
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
|
||||
const MachineInstr *MI) const;
|
||||
bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
|
||||
unsigned getInvertedPredicatedOpcode(const int Opc) const;
|
||||
int getMaxValue(const MachineInstr *MI) const;
|
||||
unsigned getMemAccessSize(const MachineInstr* MI) const;
|
||||
int getMinValue(const MachineInstr *MI) const;
|
||||
short getNonExtOpcode(const MachineInstr *MI) const;
|
||||
bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
|
||||
unsigned &PredRegPos, unsigned &PredRegFlags) const;
|
||||
short getPseudoInstrPair(MachineInstr *MI) const;
|
||||
short getRegForm(const MachineInstr *MI) const;
|
||||
unsigned getSize(const MachineInstr *MI) const;
|
||||
uint64_t getType(const MachineInstr* MI) const;
|
||||
unsigned getUnits(const MachineInstr* MI) const;
|
||||
unsigned getValidSubTargets(const unsigned Opcode) const;
|
||||
|
||||
|
||||
/// getInstrTimingClassLatency - Compute the instruction latency of a given
|
||||
/// instruction using Timing Class information, if available.
|
||||
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
|
||||
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
|
||||
|
||||
|
||||
void immediateExtend(MachineInstr *MI) const;
|
||||
bool isConstExtended(const MachineInstr *MI) const;
|
||||
unsigned getSize(const MachineInstr *MI) const;
|
||||
int getDotNewPredJumpOp(MachineInstr *MI,
|
||||
const MachineBranchProbabilityInfo *MBPI) const;
|
||||
unsigned getAddrMode(const MachineInstr* MI) const;
|
||||
bool isOperandExtended(const MachineInstr *MI,
|
||||
unsigned short OperandNum) const;
|
||||
unsigned short getCExtOpNum(const MachineInstr *MI) const;
|
||||
int getMinValue(const MachineInstr *MI) const;
|
||||
int getMaxValue(const MachineInstr *MI) const;
|
||||
bool NonExtEquivalentExists (const MachineInstr *MI) const;
|
||||
short getNonExtOpcode(const MachineInstr *MI) const;
|
||||
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
|
||||
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
|
||||
bool isEndLoopN(Opcode_t Opcode) const;
|
||||
bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
|
||||
unsigned &PredRegPos, unsigned &PredRegFlags) const;
|
||||
int getCondOpcode(int Opc, bool sense) const;
|
||||
|
||||
bool invertAndChangeJumpTarget(MachineInstr* MI,
|
||||
MachineBasicBlock* NewTarget) const;
|
||||
void genAllInsnTimingClasses(MachineFunction &MF) const;
|
||||
bool reversePredSense(MachineInstr* MI) const;
|
||||
unsigned reversePrediction(unsigned Opcode) const;
|
||||
bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@ -92,6 +92,7 @@ namespace {
|
||||
/// \brief A handle to the branch probability pass.
|
||||
const MachineBranchProbabilityInfo *MBPI;
|
||||
|
||||
bool isNewValueJumpCandidate(const MachineInstr *MI) const;
|
||||
};
|
||||
|
||||
} // end of anonymous namespace
|
||||
@ -280,9 +281,9 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
|
||||
return true;
|
||||
}
|
||||
|
||||
// Given a compare operator, return a matching New Value Jump
|
||||
// compare operator. Make sure that MI here is included in
|
||||
// HexagonInstrInfo.cpp::isNewValueJumpCandidate
|
||||
|
||||
// Given a compare operator, return a matching New Value Jump compare operator.
|
||||
// Make sure that MI here is included in isNewValueJumpCandidate.
|
||||
static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
|
||||
bool secondRegNewified,
|
||||
MachineBasicBlock *jmpTarget,
|
||||
@ -348,6 +349,26 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool HexagonNewValueJump::isNewValueJumpCandidate(const MachineInstr *MI)
|
||||
const {
|
||||
switch (MI->getOpcode()) {
|
||||
case Hexagon::C2_cmpeq:
|
||||
case Hexagon::C2_cmpeqi:
|
||||
case Hexagon::C2_cmpgt:
|
||||
case Hexagon::C2_cmpgti:
|
||||
case Hexagon::C2_cmpgtu:
|
||||
case Hexagon::C2_cmpgtui:
|
||||
case Hexagon::C4_cmpneq:
|
||||
case Hexagon::C4_cmplte:
|
||||
case Hexagon::C4_cmplteu:
|
||||
return true;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
|
||||
@ -468,7 +489,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
|
||||
MI->getOperand(0).getReg() == predReg) {
|
||||
|
||||
// Not all compares can be new value compare. Arch Spec: 7.6.1.1
|
||||
if (QII->isNewValueJumpCandidate(MI)) {
|
||||
if (isNewValueJumpCandidate(MI)) {
|
||||
|
||||
assert((MI->getDesc().isCompare()) &&
|
||||
"Only compare instruction can be collapsed into New Value Jump");
|
||||
@ -591,8 +612,8 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
|
||||
DebugLoc dl = MI->getDebugLoc();
|
||||
MachineInstr *NewMI;
|
||||
|
||||
assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
|
||||
"This compare is not a New Value Jump candidate.");
|
||||
assert((isNewValueJumpCandidate(cmpInstr)) &&
|
||||
"This compare is not a New Value Jump candidate.");
|
||||
unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
|
||||
isSecondOpNewified,
|
||||
jmpTarget, MBPI);
|
||||
|
||||
@ -35,7 +35,7 @@ def SLOT_ENDLOOP: FuncUnit;
|
||||
|
||||
// Itinerary classes.
|
||||
def PSEUDO : InstrItinClass;
|
||||
def PSEUDOM : InstrItinClass;
|
||||
def PSEUDOM : InstrItinClass;
|
||||
// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
|
||||
def DUPLEX : InstrItinClass;
|
||||
def PREFIX : InstrItinClass;
|
||||
|
||||
@ -24,10 +24,6 @@ using namespace llvm;
|
||||
#define GET_SUBTARGETINFO_TARGET_DESC
|
||||
#include "HexagonGenSubtargetInfo.inc"
|
||||
|
||||
static cl::opt<bool>
|
||||
EnableV3("enable-hexagon-v3", cl::Hidden,
|
||||
cl::desc("Enable Hexagon V3 instructions."));
|
||||
|
||||
static cl::opt<bool>
|
||||
EnableMemOps(
|
||||
"enable-hexagon-memops",
|
||||
@ -48,6 +44,9 @@ EnableIEEERndNear(
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(false),
|
||||
cl::desc("Generate non-chopped conversion from fp to int."));
|
||||
|
||||
static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(true));
|
||||
|
||||
static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
|
||||
cl::Hidden, cl::ZeroOrMore, cl::init(false),
|
||||
cl::desc("Disable Hexagon MI Scheduling"));
|
||||
@ -91,6 +90,8 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
|
||||
ModeIEEERndNear = true;
|
||||
else
|
||||
ModeIEEERndNear = false;
|
||||
|
||||
UseBSBScheduling = hasV60TOps() && EnableBSBSched;
|
||||
}
|
||||
|
||||
// Pin the vtable to this file.
|
||||
|
||||
@ -43,6 +43,10 @@ public:
|
||||
};
|
||||
|
||||
HexagonArchEnum HexagonArchVersion;
|
||||
/// True if the target should use Back-Skip-Back scheduling. This is the
|
||||
/// default for V60.
|
||||
bool UseBSBScheduling;
|
||||
|
||||
private:
|
||||
std::string CPUString;
|
||||
HexagonInstrInfo InstrInfo;
|
||||
@ -89,6 +93,8 @@ public:
|
||||
bool modeIEEERndNear() const { return ModeIEEERndNear; }
|
||||
bool useHVXDblOps() const { return UseHVXDblOps; }
|
||||
bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
|
||||
|
||||
bool useBSBScheduling() const { return UseBSBScheduling; }
|
||||
bool enableMachineScheduler() const override;
|
||||
// Always use the TargetLowering default scheduler.
|
||||
// FIXME: This will use the vliw scheduler which is probably just hurting
|
||||
|
||||
@ -432,9 +432,9 @@ bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
|
||||
|
||||
int NewOpcode;
|
||||
if (RC == &Hexagon::PredRegsRegClass)
|
||||
NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
|
||||
NewOpcode = QII->getDotNewPredOp(MI, MBPI);
|
||||
else
|
||||
NewOpcode = QII->GetDotNewOp(MI);
|
||||
NewOpcode = QII->getDotNewOp(MI);
|
||||
MI->setDesc(QII->get(NewOpcode));
|
||||
|
||||
return true;
|
||||
@ -442,7 +442,7 @@ bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
|
||||
|
||||
bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
|
||||
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
|
||||
int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
|
||||
int NewOpcode = QII->getDotOldOp(MI->getOpcode());
|
||||
MI->setDesc(QII->get(NewOpcode));
|
||||
return true;
|
||||
}
|
||||
@ -757,7 +757,7 @@ bool HexagonPacketizerList::CanPromoteToDotNew(
|
||||
else {
|
||||
// Create a dot new machine instruction to see if resources can be
|
||||
// allocated. If not, bail out now.
|
||||
int NewOpcode = QII->GetDotNewOp(MI);
|
||||
int NewOpcode = QII->getDotNewOp(MI);
|
||||
const MCInstrDesc &desc = QII->get(NewOpcode);
|
||||
DebugLoc dl;
|
||||
MachineInstr *NewMI =
|
||||
|
||||
@ -191,7 +191,15 @@ namespace HexagonII {
|
||||
|
||||
// Which operand consumes or produces a new value.
|
||||
NewValueOpPos2 = 51,
|
||||
NewValueOpMask2 = 0x7
|
||||
NewValueOpMask2 = 0x7,
|
||||
|
||||
// Accumulator instructions.
|
||||
AccumulatorPos = 54,
|
||||
AccumulatorMask = 0x1,
|
||||
|
||||
// Complex XU, prevent xu competition by prefering slot3
|
||||
PrefersSlot3Pos = 55,
|
||||
PrefersSlot3Mask = 0x1,
|
||||
};
|
||||
|
||||
// *** The code above must match HexagonInstrFormat*.td *** //
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user