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[globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317132 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2017-11-01 22:13:05 +00:00
parent d005962cad
commit 8ec459f49c
3 changed files with 19 additions and 0 deletions
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2
include/llvm/TableGen/Error.h
View File

@ -19,6 +19,8 @@
namespace llvm {
void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg);
void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg);
void PrintWarning(const char *Loc, const Twine &Msg);
void PrintWarning(const Twine &Msg);

4
lib/TableGen/Error.cpp
View File

@ -39,6 +39,10 @@ static void PrintMessage(ArrayRef<SMLoc> Loc, SourceMgr::DiagKind Kind,
"instantiated from multiclass");
}
void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg) {
PrintMessage(NoteLoc, SourceMgr::DK_Note, Msg);
}
void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg) {
PrintMessage(WarningLoc, SourceMgr::DK_Warning, Msg);
}

13
utils/TableGen/RegisterBankEmitter.cpp
View File

@ -299,6 +299,19 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
Banks.push_back(Bank);
}
// Warn about ambiguous MIR caused by register bank/class name clashes.
for (const auto &Class : Records.getAllDerivedDefinitions("RegisterClass")) {
for (const auto &Bank : Banks) {
if (Bank.getName().lower() == Class->getName().lower()) {
PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
"distinct from register classes "
"to avoid ambiguous MIR");
PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
PrintNote(Class->getLoc(), "RegisterClass was declared here");
}
}
}
emitSourceFileHeader("Register Bank Source Fragments", OS);
OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
<< "#undef GET_REGBANK_DECLARATIONS\n";