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Don't assume the registers will be enumerated sequentially.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2013-05-29 20:42:21 +00:00
parent 745825f582
commit 8ed5506e85
1 changed files with 5 additions and 2 deletions
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7
lib/Target/X86/X86RegisterInfo.cpp
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@ -373,8 +373,11 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(*AI);
// XMM8, XMM9, ...
assert(X86::XMM15 == X86::XMM8+7);
for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
static const uint16_t XMMReg[] = {
X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11,
X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
};
for (MCRegAliasIterator AI(XMMReg[n], this, true); AI.isValid(); ++AI)
Reserved.set(*AI);
}
}