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It seems that OR operation does not affect status reg at all.

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Remove impdef of SRW. This fixes PR4779


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83739 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-10-10 22:17:47 +00:00
parent 558c36729f
commit 8f8e9f0830
2 changed files with 22 additions and 12 deletions
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20
lib/Target/MSP430/MSP430InstrInfo.td
View File

@ -671,30 +671,26 @@ def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
let isTwoAddress = 0 in {
def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"bis.b\t{$src, $dst}",
[(store (or (load addr:$dst), GR8:$src), addr:$dst),
(implicit SRW)]>;
[(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
"bis.w\t{$src, $dst}",
[(store (or (load addr:$dst), GR16:$src), addr:$dst),
(implicit SRW)]>;
[(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
"bis.b\t{$src, $dst}",
[(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
(implicit SRW)]>;
[(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
"bis.w\t{$src, $dst}",
[(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
(implicit SRW)]>;
[(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bis.b\t{$src, $dst}",
[(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
(implicit SRW)]>;
[(store (or (i8 (load addr:$dst)),
(i8 (load addr:$src))), addr:$dst)]>;
def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bis.w\t{$src, $dst}",
[(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
(implicit SRW)]>;
[(store (or (i16 (load addr:$dst)),
(i16 (load addr:$src))), addr:$dst)]>;
}
} // isTwoAddress = 1

14
test/CodeGen/MSP430/2009-10-10-OrImpDef.ll Normal file
View File

@ -0,0 +1,14 @@
; RUN: llc -march=msp430 < %s
; PR4779
define void @foo() nounwind {
entry:
%r = alloca i8 ; <i8*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
volatile load i8* %r, align 1 ; <i8>:0 [#uses=1]
or i8 %0, 1 ; <i8>:1 [#uses=1]
volatile store i8 %1, i8* %r, align 1
br label %return
return: ; preds = %entry
ret void
}