mirror of
https://github.com/RPCS3/llvm.git
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[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eugene Zelenko
parent
8e66c2eabb
commit
8fd05041c0
@ -1,4 +1,4 @@
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//===-- MachineSSAUpdater.h - Unstructured SSA Update Tool ------*- C++ -*-===//
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//===- MachineSSAUpdater.h - Unstructured SSA Update Tool -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -14,18 +14,17 @@
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#ifndef LLVM_CODEGEN_MACHINESSAUPDATER_H
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#define LLVM_CODEGEN_MACHINESSAUPDATER_H
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#include "llvm/Support/Compiler.h"
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namespace llvm {
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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template<typename T> class SmallVectorImpl;
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template<typename T> class SSAUpdaterTraits;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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template<typename T> class SmallVectorImpl;
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template<typename T> class SSAUpdaterTraits;
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/// MachineSSAUpdater - This class updates SSA form for a set of virtual
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/// registers defined in multiple blocks. This is used when code duplication
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@ -38,7 +37,7 @@ private:
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/// AvailableVals - This keeps track of which value to use on a per-block
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/// basis. When we insert PHI nodes, we keep track of them here.
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//typedef DenseMap<MachineBasicBlock*, unsigned > AvailableValsTy;
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void *AV;
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void *AV = nullptr;
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/// VR - Current virtual register whose uses are being updated.
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unsigned VR;
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@ -52,11 +51,14 @@ private:
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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public:
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/// MachineSSAUpdater constructor. If InsertedPHIs is specified, it will be
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/// filled in with all PHI Nodes created by rewriting.
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explicit MachineSSAUpdater(MachineFunction &MF,
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SmallVectorImpl<MachineInstr*> *InsertedPHIs = nullptr);
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MachineSSAUpdater(const MachineSSAUpdater &) = delete;
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MachineSSAUpdater &operator=(const MachineSSAUpdater &) = delete;
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~MachineSSAUpdater();
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/// Initialize - Reset this object to get ready for a new set of SSA
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@ -93,7 +95,6 @@ public:
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/// their respective blocks. However, the use of X happens in the *middle* of
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/// a block. Because of this, we need to insert a new PHI node in SomeBB to
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/// merge the appropriate values, and this value isn't live out of the block.
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///
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unsigned GetValueInMiddleOfBlock(MachineBasicBlock *BB);
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/// RewriteUse - Rewrite a use of the symbolic value. This handles PHI nodes,
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@ -105,11 +106,8 @@ public:
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private:
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unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB);
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void operator=(const MachineSSAUpdater&) = delete;
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MachineSSAUpdater(const MachineSSAUpdater&) = delete;
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};
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} // End llvm namespace
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} // end namespace llvm
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#endif
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#endif // LLVM_CODEGEN_MACHINESSAUPDATER_H
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@ -52,13 +52,13 @@
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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namespace llvm {
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class AnalysisUsage;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineLoop;
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@ -1,4 +1,4 @@
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//===-- MachinePipeliner.cpp - Machine Software Pipeliner Pass ------------===//
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//===- MachinePipeliner.cpp - Machine Software Pipeliner Pass -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -80,7 +80,6 @@
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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@ -92,15 +91,19 @@
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/PassRegistry.h"
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#include "llvm/PassSupport.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm>
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@ -111,6 +114,7 @@
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#include <functional>
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#include <iterator>
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#include <map>
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#include <memory>
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#include <tuple>
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#include <utility>
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#include <vector>
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@ -169,7 +173,6 @@ namespace {
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class NodeSet;
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class SMSchedule;
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class SwingSchedulerDAG;
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/// The main class in the implementation of the target independent
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/// software pipeliner pass.
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@ -185,6 +188,7 @@ public:
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#ifndef NDEBUG
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static int NumTries;
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#endif
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/// Cache the target analysis information about the loop.
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struct LoopInfo {
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MachineBasicBlock *TBB = nullptr;
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@ -196,6 +200,7 @@ public:
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LoopInfo LI;
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static char ID;
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MachinePipeliner() : MachineFunctionPass(ID) {
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initializeMachinePipelinerPass(*PassRegistry::getPassRegistry());
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}
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@ -222,9 +227,9 @@ private:
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class SwingSchedulerDAG : public ScheduleDAGInstrs {
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MachinePipeliner &Pass;
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/// The minimum initiation interval between iterations for this schedule.
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unsigned MII;
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unsigned MII = 0;
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/// Set to true if a valid pipelined schedule is found for the loop.
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bool Scheduled;
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bool Scheduled = false;
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MachineLoop &Loop;
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LiveIntervals &LIS;
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const RegisterClassInfo &RegClassInfo;
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@ -234,9 +239,10 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
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ScheduleDAGTopologicalSort Topo;
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struct NodeInfo {
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int ASAP;
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int ALAP;
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NodeInfo() : ASAP(0), ALAP(0) {}
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int ASAP = 0;
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int ALAP = 0;
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NodeInfo() = default;
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};
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/// Computed properties for each node in the graph.
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std::vector<NodeInfo> ScheduleInfo;
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@ -245,10 +251,10 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
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/// Computed node ordering for scheduling.
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SetVector<SUnit *> NodeOrder;
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typedef SmallVector<NodeSet, 8> NodeSetType;
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typedef DenseMap<unsigned, unsigned> ValueMapTy;
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typedef SmallVectorImpl<MachineBasicBlock *> MBBVectorTy;
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typedef DenseMap<MachineInstr *, MachineInstr *> InstrMapTy;
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using NodeSetType = SmallVector<NodeSet, 8>;
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using ValueMapTy = DenseMap<unsigned, unsigned>;
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using MBBVectorTy = SmallVectorImpl<MachineBasicBlock *>;
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using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
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/// Instructions to change when emitting the final schedule.
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DenseMap<SUnit *, std::pair<unsigned, int64_t>> InstrChanges;
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@ -272,8 +278,8 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
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public:
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Circuits(std::vector<SUnit> &SUs)
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: SUnits(SUs), Stack(), Blocked(SUs.size()), B(SUs.size()),
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AdjK(SUs.size()) {}
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: SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {}
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/// Reset the data structures used in the circuit algorithm.
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void reset() {
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Stack.clear();
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@ -281,6 +287,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
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B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
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NumPaths = 0;
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}
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void createAdjacencyStructure(SwingSchedulerDAG *DAG);
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bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false);
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void unblock(int U);
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@ -289,9 +296,8 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
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public:
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SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis,
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const RegisterClassInfo &rci)
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: ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), MII(0),
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Scheduled(false), Loop(L), LIS(lis), RegClassInfo(rci),
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Topo(SUnits, &ExitSU) {
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: ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
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RegClassInfo(rci), Topo(SUnits, &ExitSU) {
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P.MF->getSubtarget().getSMSMutations(Mutations);
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}
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@ -455,7 +461,7 @@ private:
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/// that assigns a priority to the set.
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class NodeSet {
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SetVector<SUnit *> Nodes;
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bool HasRecurrence;
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bool HasRecurrence = false;
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unsigned RecMII = 0;
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int MaxMOV = 0;
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int MaxDepth = 0;
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@ -463,10 +469,9 @@ class NodeSet {
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SUnit *ExceedPressure = nullptr;
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public:
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typedef SetVector<SUnit *>::const_iterator iterator;
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NodeSet() : Nodes(), HasRecurrence(false) {}
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using iterator = SetVector<SUnit *>::const_iterator;
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NodeSet() = default;
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NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {}
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bool insert(SUnit *SU) { return Nodes.insert(SU); }
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@ -581,13 +586,13 @@ private:
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/// Keep track of the first cycle value in the schedule. It starts
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/// as zero, but the algorithm allows negative values.
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int FirstCycle;
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int FirstCycle = 0;
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/// Keep track of the last cycle value in the schedule.
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int LastCycle;
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int LastCycle = 0;
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/// The initiation interval (II) for the schedule.
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int InitiationInterval;
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int InitiationInterval = 0;
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/// Target machine information.
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const TargetSubtargetInfo &ST;
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@ -600,11 +605,7 @@ private:
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public:
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SMSchedule(MachineFunction *mf)
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: ST(mf->getSubtarget()), MRI(mf->getRegInfo()),
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Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) {
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FirstCycle = 0;
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LastCycle = 0;
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InitiationInterval = 0;
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}
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Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) {}
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void reset() {
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ScheduledInstrs.clear();
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@ -638,9 +639,9 @@ public:
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bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
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/// Iterators for the cycle to instruction map.
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typedef DenseMap<int, std::deque<SUnit *>>::iterator sched_iterator;
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typedef DenseMap<int, std::deque<SUnit *>>::const_iterator
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const_sched_iterator;
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using sched_iterator = DenseMap<int, std::deque<SUnit *>>::iterator;
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using const_sched_iterator =
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DenseMap<int, std::deque<SUnit *>>::const_iterator;
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/// Return true if the instruction is scheduled at the specified stage.
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bool isScheduledAtStage(SUnit *SU, unsigned StageNum) {
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@ -715,6 +716,7 @@ char MachinePipeliner::ID = 0;
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int MachinePipeliner::NumTries = 0;
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#endif
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char &llvm::MachinePipelinerID = MachinePipeliner::ID;
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INITIALIZE_PASS_BEGIN(MachinePipeliner, DEBUG_TYPE,
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"Modulo Software Pipelining", false, false)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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@ -1256,6 +1258,8 @@ struct FuncUnitSorter {
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const InstrItineraryData *InstrItins;
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DenseMap<unsigned, unsigned> Resources;
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FuncUnitSorter(const InstrItineraryData *IID) : InstrItins(IID) {}
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// Compute the number of functional unit alternatives needed
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// at each stage, and take the minimum value. We prioritize the
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// instructions by the least number of choices first.
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@ -1291,7 +1295,6 @@ struct FuncUnitSorter {
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}
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}
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FuncUnitSorter(const InstrItineraryData *IID) : InstrItins(IID) {}
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/// Return true if IS1 has less priority than IS2.
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bool operator()(const MachineInstr *IS1, const MachineInstr *IS2) const {
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unsigned F1 = 0, F2 = 0;
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@ -1384,7 +1387,7 @@ unsigned SwingSchedulerDAG::calculateRecMII(NodeSetType &NodeSets) {
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unsigned RecMII = 0;
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for (NodeSet &Nodes : NodeSets) {
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if (Nodes.size() == 0)
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if (Nodes.empty())
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continue;
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unsigned Delay = Nodes.size() - 1;
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@ -1554,7 +1557,6 @@ static bool ignoreDependence(const SDep &D, bool isPred) {
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/// D - Depth of each node.
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/// H - Height of each node.
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void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
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ScheduleInfo.resize(SUnits.size());
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DEBUG({
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@ -1651,7 +1653,7 @@ static bool pred_L(SetVector<SUnit *> &NodeOrder,
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Preds.insert(IS->getSUnit());
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}
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}
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return Preds.size() > 0;
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return !Preds.empty();
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}
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/// Compute the Succ_L(O) set, as defined in the paper. The set is defined
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@ -1683,7 +1685,7 @@ static bool succ_L(SetVector<SUnit *> &NodeOrder,
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Succs.insert(PI->getSUnit());
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}
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}
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return Succs.size() > 0;
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return !Succs.empty();
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}
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/// Return true if there is a path from the specified node to any of the nodes
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@ -1868,7 +1870,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
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Visited.clear();
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computePath(NI, Path, NodesAdded, I, Visited);
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}
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if (Path.size() > 0)
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if (!Path.empty())
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I.insert(Path.begin(), Path.end());
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}
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// Add the nodes from the previous node set to the current node set.
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@ -1879,7 +1881,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
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Visited.clear();
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computePath(NI, Path, I, NodesAdded, Visited);
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}
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if (Path.size() > 0)
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if (!Path.empty())
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I.insert(Path.begin(), Path.end());
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}
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NodesAdded.insert(I.begin(), I.end());
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@ -1892,7 +1894,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
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if (succ_L(NodesAdded, N))
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for (SUnit *I : N)
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addConnectedNodes(I, NewSet, NodesAdded);
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if (NewSet.size() > 0)
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if (!NewSet.empty())
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NodeSets.push_back(NewSet);
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// Create a new node set with the connected nodes of any predecessor of a node
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@ -1901,7 +1903,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
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if (pred_L(NodesAdded, N))
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for (SUnit *I : N)
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addConnectedNodes(I, NewSet, NodesAdded);
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if (NewSet.size() > 0)
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if (!NewSet.empty())
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NodeSets.push_back(NewSet);
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// Create new nodes sets with the connected nodes any any remaining node that
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@ -1911,7 +1913,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
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if (NodesAdded.count(SU) == 0) {
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NewSet.clear();
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addConnectedNodes(SU, NewSet, NodesAdded);
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if (NewSet.size() > 0)
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if (!NewSet.empty())
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NodeSets.push_back(NewSet);
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}
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}
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@ -1976,7 +1978,7 @@ void SwingSchedulerDAG::removeDuplicateNodes(NodeSetType &NodeSets) {
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for (NodeSetType::iterator J = I + 1; J != E;) {
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J->remove_if([&](SUnit *SUJ) { return I->count(SUJ); });
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if (J->size() == 0) {
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if (J->empty()) {
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NodeSets.erase(J);
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E = NodeSets.end();
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} else {
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@ -2147,8 +2149,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
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/// Process the nodes in the computed order and create the pipelined schedule
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/// of the instructions, if possible. Return true if a schedule is found.
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bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
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if (NodeOrder.size() == 0)
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if (NodeOrder.empty())
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return false;
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bool scheduleFound = false;
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@ -2325,7 +2326,7 @@ void SwingSchedulerDAG::generateProlog(SMSchedule &Schedule, unsigned LastStage,
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ValueMapTy *VRMap,
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MBBVectorTy &PrologBBs) {
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MachineBasicBlock *PreheaderBB = MLI->getLoopFor(BB)->getLoopPreheader();
|
||||
assert(PreheaderBB != NULL &&
|
||||
assert(PreheaderBB != nullptr &&
|
||||
"Need to add code to handle loops w/o preheader");
|
||||
MachineBasicBlock *PredBB = PreheaderBB;
|
||||
InstrMapTy InstrMap;
|
||||
|
||||
@ -15,31 +15,36 @@
|
||||
#include "llvm/CodeGen/MachineSSAUpdater.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/IR/DebugLoc.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetOpcodes.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include "llvm/Transforms/Utils/SSAUpdaterImpl.h"
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "machine-ssaupdater"
|
||||
|
||||
typedef DenseMap<MachineBasicBlock*, unsigned> AvailableValsTy;
|
||||
using AvailableValsTy = DenseMap<MachineBasicBlock *, unsigned>;
|
||||
|
||||
static AvailableValsTy &getAvailableVals(void *AV) {
|
||||
return *static_cast<AvailableValsTy*>(AV);
|
||||
}
|
||||
|
||||
MachineSSAUpdater::MachineSSAUpdater(MachineFunction &MF,
|
||||
SmallVectorImpl<MachineInstr*> *NewPHI)
|
||||
: AV(nullptr), InsertedPHIs(NewPHI) {
|
||||
TII = MF.getSubtarget().getInstrInfo();
|
||||
MRI = &MF.getRegInfo();
|
||||
}
|
||||
: InsertedPHIs(NewPHI), TII(MF.getSubtarget().getInstrInfo()),
|
||||
MRI(&MF.getRegInfo()) {}
|
||||
|
||||
MachineSSAUpdater::~MachineSSAUpdater() {
|
||||
delete static_cast<AvailableValsTy*>(AV);
|
||||
@ -77,7 +82,7 @@ unsigned MachineSSAUpdater::GetValueAtEndOfBlock(MachineBasicBlock *BB) {
|
||||
|
||||
static
|
||||
unsigned LookForIdenticalPHI(MachineBasicBlock *BB,
|
||||
SmallVectorImpl<std::pair<MachineBasicBlock*, unsigned> > &PredValues) {
|
||||
SmallVectorImpl<std::pair<MachineBasicBlock *, unsigned>> &PredValues) {
|
||||
if (BB->empty())
|
||||
return 0;
|
||||
|
||||
@ -136,7 +141,6 @@ MachineInstrBuilder InsertNewDef(unsigned Opcode,
|
||||
/// their respective blocks. However, the use of X happens in the *middle* of
|
||||
/// a block. Because of this, we need to insert a new PHI node in SomeBB to
|
||||
/// merge the appropriate values, and this value isn't live out of the block.
|
||||
///
|
||||
unsigned MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB) {
|
||||
// If there is no definition of the renamed variable in this block, just use
|
||||
// GetValueAtEndOfBlock to do our work.
|
||||
@ -233,14 +237,15 @@ void MachineSSAUpdater::RewriteUse(MachineOperand &U) {
|
||||
/// SSAUpdaterTraits<MachineSSAUpdater> - Traits for the SSAUpdaterImpl
|
||||
/// template, specialized for MachineSSAUpdater.
|
||||
namespace llvm {
|
||||
|
||||
template<>
|
||||
class SSAUpdaterTraits<MachineSSAUpdater> {
|
||||
public:
|
||||
typedef MachineBasicBlock BlkT;
|
||||
typedef unsigned ValT;
|
||||
typedef MachineInstr PhiT;
|
||||
using BlkT = MachineBasicBlock;
|
||||
using ValT = unsigned;
|
||||
using PhiT = MachineInstr;
|
||||
using BlkSucc_iterator = MachineBasicBlock::succ_iterator;
|
||||
|
||||
typedef MachineBasicBlock::succ_iterator BlkSucc_iterator;
|
||||
static BlkSucc_iterator BlkSucc_begin(BlkT *BB) { return BB->succ_begin(); }
|
||||
static BlkSucc_iterator BlkSucc_end(BlkT *BB) { return BB->succ_end(); }
|
||||
|
||||
@ -259,12 +264,16 @@ public:
|
||||
PHI_iterator &operator++() { idx += 2; return *this; }
|
||||
bool operator==(const PHI_iterator& x) const { return idx == x.idx; }
|
||||
bool operator!=(const PHI_iterator& x) const { return !operator==(x); }
|
||||
|
||||
unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
|
||||
|
||||
MachineBasicBlock *getIncomingBlock() {
|
||||
return PHI->getOperand(idx+1).getMBB();
|
||||
}
|
||||
};
|
||||
|
||||
static inline PHI_iterator PHI_begin(PhiT *PHI) { return PHI_iterator(PHI); }
|
||||
|
||||
static inline PHI_iterator PHI_end(PhiT *PHI) {
|
||||
return PHI_iterator(PHI, true);
|
||||
}
|
||||
@ -309,7 +318,6 @@ public:
|
||||
}
|
||||
|
||||
/// InstrIsPHI - Check if an instruction is a PHI.
|
||||
///
|
||||
static MachineInstr *InstrIsPHI(MachineInstr *I) {
|
||||
if (I && I->isPHI())
|
||||
return I;
|
||||
@ -338,7 +346,7 @@ public:
|
||||
}
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
} // end namespace llvm
|
||||
|
||||
/// GetValueAtEndOfBlockInternal - Check to see if AvailableVals has an entry
|
||||
/// for the specified BB and if so, return it. If not, construct SSA form by
|
||||
|
||||
@ -200,8 +200,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
|
||||
INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
|
||||
"Machine Instruction Scheduler", false, false)
|
||||
|
||||
MachineScheduler::MachineScheduler()
|
||||
: MachineSchedulerBase(ID) {
|
||||
MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
|
||||
initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
@ -225,8 +224,7 @@ char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
|
||||
INITIALIZE_PASS(PostMachineScheduler, "postmisched",
|
||||
"PostRA Machine Instruction Scheduler", false, false)
|
||||
|
||||
PostMachineScheduler::PostMachineScheduler()
|
||||
: MachineSchedulerBase(ID) {
|
||||
PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
|
||||
initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
@ -448,12 +446,14 @@ struct SchedRegion {
|
||||
MachineBasicBlock::iterator RegionBegin;
|
||||
MachineBasicBlock::iterator RegionEnd;
|
||||
unsigned NumRegionInstrs;
|
||||
|
||||
SchedRegion(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E,
|
||||
unsigned N) :
|
||||
RegionBegin(B), RegionEnd(E), NumRegionInstrs(N) {}
|
||||
};
|
||||
|
||||
typedef SmallVector<SchedRegion, 16> MBBRegionsVector;
|
||||
using MBBRegionsVector = SmallVector<SchedRegion, 16>;
|
||||
|
||||
static void
|
||||
getSchedRegions(MachineBasicBlock *MBB,
|
||||
MBBRegionsVector &Regions,
|
||||
@ -1589,7 +1589,6 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
|
||||
|
||||
/// \brief Callback from DAG postProcessing to create cluster edges for loads.
|
||||
void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
|
||||
|
||||
ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
|
||||
|
||||
// Map DAG NodeNum to store chain ID.
|
||||
@ -1635,6 +1634,7 @@ namespace {
|
||||
class CopyConstrain : public ScheduleDAGMutation {
|
||||
// Transient state.
|
||||
SlotIndex RegionBeginIdx;
|
||||
|
||||
// RegionEndIdx is the slot index of the last non-debug instruction in the
|
||||
// scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
|
||||
SlotIndex RegionEndIdx;
|
||||
@ -3247,7 +3247,6 @@ void PostGenericScheduler::registerRoots() {
|
||||
/// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
|
||||
void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
|
||||
SchedCandidate &TryCand) {
|
||||
|
||||
// Initialize the candidate if needed.
|
||||
if (!Cand.isValid()) {
|
||||
TryCand.Reason = NodeOrder;
|
||||
@ -3486,6 +3485,7 @@ class InstructionShuffler : public MachineSchedStrategy {
|
||||
// instructions to be scheduled first.
|
||||
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false>>
|
||||
TopQ;
|
||||
|
||||
// When scheduling bottom-up, use greater-than as the queue priority.
|
||||
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true>>
|
||||
BottomQ;
|
||||
@ -3602,6 +3602,7 @@ struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
|
||||
SS << " I:" << DFS->getNumInstrs(SU);
|
||||
return SS.str();
|
||||
}
|
||||
|
||||
static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
|
||||
return G->getGraphNodeLabel(SU);
|
||||
}
|
||||
@ -3625,7 +3626,6 @@ struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
|
||||
|
||||
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
|
||||
/// rendered using 'dot'.
|
||||
///
|
||||
void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
|
||||
#ifndef NDEBUG
|
||||
ViewGraph(this, Name, false, Title);
|
||||
|
||||
@ -22,13 +22,13 @@
|
||||
#include "llvm/CodeGen/MachineLoopInfo.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/TargetSchedule.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/Format.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
@ -42,6 +42,7 @@ using namespace llvm;
|
||||
#define DEBUG_TYPE "machine-trace-metrics"
|
||||
|
||||
char MachineTraceMetrics::ID = 0;
|
||||
|
||||
char &llvm::MachineTraceMetricsID = MachineTraceMetrics::ID;
|
||||
|
||||
INITIALIZE_PASS_BEGIN(MachineTraceMetrics, DEBUG_TYPE,
|
||||
@ -945,7 +946,7 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
|
||||
return Height;
|
||||
}
|
||||
|
||||
typedef DenseMap<const MachineInstr *, unsigned> MIHeightMap;
|
||||
using MIHeightMap = DenseMap<const MachineInstr *, unsigned>;
|
||||
|
||||
// Push the height of DefMI upwards if required to match UseMI.
|
||||
// Return true if this is the first time DefMI was seen.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
|
||||
//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -23,41 +23,68 @@
|
||||
// the verifier errors.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/DenseSet.h"
|
||||
#include "llvm/ADT/DepthFirstIterator.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/SetOperations.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/ADT/Twine.h"
|
||||
#include "llvm/Analysis/EHPersonalities.h"
|
||||
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
|
||||
#include "llvm/CodeGen/LiveInterval.h"
|
||||
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
||||
#include "llvm/CodeGen/LiveStackAnalysis.h"
|
||||
#include "llvm/CodeGen/LiveVariables.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBundle.h"
|
||||
#include "llvm/CodeGen/MachineMemOperand.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/CodeGen/PseudoSourceValue.h"
|
||||
#include "llvm/CodeGen/SlotIndexes.h"
|
||||
#include "llvm/CodeGen/StackMaps.h"
|
||||
#include "llvm/IR/BasicBlock.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/InlineAsm.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/MC/LaneBitmask.h"
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/MC/MCInstrDesc.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/MC/MCTargetOptions.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/FileSystem.h"
|
||||
#include "llvm/Support/LowLevelTypeImpl.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOpcodes.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <cstddef>
|
||||
#include <cstdint>
|
||||
#include <iterator>
|
||||
#include <string>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
namespace {
|
||||
struct MachineVerifier {
|
||||
|
||||
MachineVerifier(Pass *pass, const char *b) :
|
||||
PASS(pass),
|
||||
Banner(b)
|
||||
{}
|
||||
struct MachineVerifier {
|
||||
MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
|
||||
|
||||
unsigned verify(MachineFunction &MF);
|
||||
|
||||
@ -75,11 +102,11 @@ namespace {
|
||||
bool isFunctionRegBankSelected;
|
||||
bool isFunctionSelected;
|
||||
|
||||
typedef SmallVector<unsigned, 16> RegVector;
|
||||
typedef SmallVector<const uint32_t*, 4> RegMaskVector;
|
||||
typedef DenseSet<unsigned> RegSet;
|
||||
typedef DenseMap<unsigned, const MachineInstr*> RegMap;
|
||||
typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
|
||||
using RegVector = SmallVector<unsigned, 16>;
|
||||
using RegMaskVector = SmallVector<const uint32_t *, 4>;
|
||||
using RegSet = DenseSet<unsigned>;
|
||||
using RegMap = DenseMap<unsigned, const MachineInstr *>;
|
||||
using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
|
||||
|
||||
const MachineInstr *FirstTerminator;
|
||||
BlockSet FunctionBlocks;
|
||||
@ -101,7 +128,7 @@ namespace {
|
||||
|
||||
struct BBInfo {
|
||||
// Is this MBB reachable from the MF entry point?
|
||||
bool reachable;
|
||||
bool reachable = false;
|
||||
|
||||
// Vregs that must be live in because they are used without being
|
||||
// defined. Map value is the user.
|
||||
@ -126,7 +153,7 @@ namespace {
|
||||
// Set versions of block's predecessor and successor lists.
|
||||
BlockSet Preds, Succs;
|
||||
|
||||
BBInfo() : reachable(false) {}
|
||||
BBInfo() = default;
|
||||
|
||||
// Add register to vregsPassed if it belongs there. Return true if
|
||||
// anything changed.
|
||||
@ -259,6 +286,7 @@ namespace {
|
||||
|
||||
struct MachineVerifierPass : public MachineFunctionPass {
|
||||
static char ID; // Pass ID, replacement for typeid
|
||||
|
||||
const std::string Banner;
|
||||
|
||||
MachineVerifierPass(std::string banner = std::string())
|
||||
@ -279,9 +307,10 @@ namespace {
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
} // end anonymous namespace
|
||||
|
||||
char MachineVerifierPass::ID = 0;
|
||||
|
||||
INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
|
||||
"Verify generated machine code", false, false)
|
||||
|
||||
@ -1466,8 +1495,7 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
|
||||
}
|
||||
}
|
||||
|
||||
void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
|
||||
}
|
||||
void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
|
||||
|
||||
// This function gets called after visiting all instructions in a bundle. The
|
||||
// argument points to the bundle header.
|
||||
@ -1952,7 +1980,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
||||
// Skip this block.
|
||||
++MFI;
|
||||
}
|
||||
for (;;) {
|
||||
while (true) {
|
||||
assert(LiveInts->isLiveInToMBB(LR, &*MFI));
|
||||
// We don't know how to track physregs into a landing pad.
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
|
||||
@ -2058,23 +2086,25 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
// FrameSetup and FrameDestroy can have zero adjustment, so using a single
|
||||
// integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
|
||||
// value is zero.
|
||||
// We use a bool plus an integer to capture the stack state.
|
||||
struct StackStateOfBB {
|
||||
StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
|
||||
ExitIsSetup(false) { }
|
||||
StackStateOfBB() = default;
|
||||
StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
|
||||
EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
|
||||
ExitIsSetup(ExitSetup) { }
|
||||
ExitIsSetup(ExitSetup) {}
|
||||
|
||||
// Can be negative, which means we are setting up a frame.
|
||||
int EntryValue;
|
||||
int ExitValue;
|
||||
bool EntryIsSetup;
|
||||
bool ExitIsSetup;
|
||||
int EntryValue = 0;
|
||||
int ExitValue = 0;
|
||||
bool EntryIsSetup = false;
|
||||
bool ExitIsSetup = false;
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
|
||||
/// by a FrameDestroy <n>, stack adjustments are identical on all
|
||||
@ -2090,8 +2120,8 @@ void MachineVerifier::verifyStackFrame() {
|
||||
df_iterator_default_set<const MachineBasicBlock*> Reachable;
|
||||
|
||||
// Visit the MBBs in DFS order.
|
||||
for (df_ext_iterator<const MachineFunction*,
|
||||
df_iterator_default_set<const MachineBasicBlock*> >
|
||||
for (df_ext_iterator<const MachineFunction *,
|
||||
df_iterator_default_set<const MachineBasicBlock *>>
|
||||
DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
|
||||
DFI != DFE; ++DFI) {
|
||||
const MachineBasicBlock *MBB = *DFI;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- OptimizePHIs.cpp - Optimize machine instruction PHIs --------------===//
|
||||
//===- OptimizePHIs.cpp - Optimize machine instruction PHIs ---------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -14,13 +14,18 @@
|
||||
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "opt-phis"
|
||||
@ -29,12 +34,14 @@ STATISTIC(NumPHICycles, "Number of PHI cycles replaced");
|
||||
STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles");
|
||||
|
||||
namespace {
|
||||
|
||||
class OptimizePHIs : public MachineFunctionPass {
|
||||
MachineRegisterInfo *MRI;
|
||||
const TargetInstrInfo *TII;
|
||||
|
||||
public:
|
||||
static char ID; // Pass identification
|
||||
|
||||
OptimizePHIs() : MachineFunctionPass(ID) {
|
||||
initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
@ -47,18 +54,21 @@ namespace {
|
||||
}
|
||||
|
||||
private:
|
||||
typedef SmallPtrSet<MachineInstr*, 16> InstrSet;
|
||||
typedef SmallPtrSetIterator<MachineInstr*> InstrSetIterator;
|
||||
using InstrSet = SmallPtrSet<MachineInstr *, 16>;
|
||||
using InstrSetIterator = SmallPtrSetIterator<MachineInstr *>;
|
||||
|
||||
bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
|
||||
InstrSet &PHIsInCycle);
|
||||
bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
|
||||
bool OptimizeBB(MachineBasicBlock &MBB);
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char OptimizePHIs::ID = 0;
|
||||
|
||||
char &llvm::OptimizePHIsID = OptimizePHIs::ID;
|
||||
|
||||
INITIALIZE_PASS(OptimizePHIs, DEBUG_TYPE,
|
||||
"Optimize machine instruction PHIs", false, false)
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
|
||||
//===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -14,24 +14,35 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "PHIEliminationUtils.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/Analysis/LoopInfo.h"
|
||||
#include "llvm/CodeGen/LiveInterval.h"
|
||||
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
||||
#include "llvm/CodeGen/LiveVariables.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineDominators.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineLoopInfo.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/CodeGen/SlotIndexes.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetOpcodes.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <iterator>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "phi-node-elimination"
|
||||
@ -51,6 +62,7 @@ static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
|
||||
cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
|
||||
|
||||
namespace {
|
||||
|
||||
class PHIElimination : public MachineFunctionPass {
|
||||
MachineRegisterInfo *MRI; // Machine register information
|
||||
LiveVariables *LV;
|
||||
@ -58,6 +70,7 @@ namespace {
|
||||
|
||||
public:
|
||||
static char ID; // Pass identification, replacement for typeid
|
||||
|
||||
PHIElimination() : MachineFunctionPass(ID) {
|
||||
initializePHIEliminationPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
@ -68,8 +81,8 @@ namespace {
|
||||
private:
|
||||
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
|
||||
/// in predecessor basic blocks.
|
||||
///
|
||||
bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
|
||||
|
||||
void LowerPHINode(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator LastPHIIt);
|
||||
|
||||
@ -78,7 +91,6 @@ namespace {
|
||||
/// register which is used in a PHI node. We map that to the BB the
|
||||
/// vreg is coming from. This is used later to determine when the vreg
|
||||
/// is killed in the BB.
|
||||
///
|
||||
void analyzePHINodes(const MachineFunction& Fn);
|
||||
|
||||
/// Split critical edges where necessary for good coalescer performance.
|
||||
@ -90,8 +102,8 @@ namespace {
|
||||
bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
|
||||
bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
|
||||
|
||||
typedef std::pair<unsigned, unsigned> BBVRegPair;
|
||||
typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
|
||||
using BBVRegPair = std::pair<unsigned, unsigned>;
|
||||
using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
|
||||
|
||||
VRegPHIUse VRegPHIUseCount;
|
||||
|
||||
@ -99,17 +111,19 @@ namespace {
|
||||
SmallPtrSet<MachineInstr*, 4> ImpDefs;
|
||||
|
||||
// Map reusable lowered PHI node -> incoming join register.
|
||||
typedef DenseMap<MachineInstr*, unsigned,
|
||||
MachineInstrExpressionTrait> LoweredPHIMap;
|
||||
using LoweredPHIMap =
|
||||
DenseMap<MachineInstr*, unsigned, MachineInstrExpressionTrait>;
|
||||
LoweredPHIMap LoweredPHIs;
|
||||
};
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
STATISTIC(NumLowered, "Number of phis lowered");
|
||||
STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
|
||||
STATISTIC(NumReused, "Number of reused lowered phis");
|
||||
|
||||
char PHIElimination::ID = 0;
|
||||
|
||||
char& llvm::PHIEliminationID = PHIElimination::ID;
|
||||
|
||||
INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
|
||||
@ -182,7 +196,6 @@ bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
|
||||
/// predecessor basic blocks.
|
||||
///
|
||||
bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) {
|
||||
if (MBB.empty() || !MBB.front().isPHI())
|
||||
@ -219,9 +232,7 @@ static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/// LowerPHINode - Lower the PHI node at the top of the specified block,
|
||||
///
|
||||
/// LowerPHINode - Lower the PHI node at the top of the specified block.
|
||||
void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator LastPHIIt) {
|
||||
++NumLowered;
|
||||
@ -534,7 +545,6 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
|
||||
/// particular, we want to map the number of uses of a virtual register which is
|
||||
/// used in a PHI node. We map that to the BB the vreg is coming from. This is
|
||||
/// used later to determine when the vreg is killed in the BB.
|
||||
///
|
||||
void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
|
||||
for (const auto &MBB : MF)
|
||||
for (const auto &BBI : MBB) {
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
|
||||
//===- PeepholeOptimizer.cpp - Peephole Optimizations ---------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -67,6 +67,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/Optional.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
@ -74,18 +75,21 @@
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineDominators.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineLoopInfo.h"
|
||||
#include "llvm/CodeGen/MachineOperand.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/MC/LaneBitmask.h"
|
||||
#include "llvm/MC/MCInstrDesc.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/Target/TargetOpcodes.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/Target/TargetSubtargetInfo.h"
|
||||
#include <cassert>
|
||||
@ -170,11 +174,11 @@ namespace {
|
||||
}
|
||||
|
||||
/// \brief Track Def -> Use info used for rewriting copies.
|
||||
typedef SmallDenseMap<TargetInstrInfo::RegSubRegPair, ValueTrackerResult>
|
||||
RewriteMapTy;
|
||||
using RewriteMapTy =
|
||||
SmallDenseMap<TargetInstrInfo::RegSubRegPair, ValueTrackerResult>;
|
||||
|
||||
/// \brief Sequence of instructions that formulate recurrence cycle.
|
||||
typedef SmallVector<RecurrenceInstr, 4> RecurrenceCycle;
|
||||
using RecurrenceCycle = SmallVector<RecurrenceInstr, 4>;
|
||||
|
||||
private:
|
||||
bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
|
||||
@ -195,6 +199,7 @@ namespace {
|
||||
bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
|
||||
SmallSet<unsigned, 4> &ImmDefRegs,
|
||||
DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
|
||||
|
||||
/// \brief Finds recurrence cycles, but only ones that formulated around
|
||||
/// a def operand and a use operand that are tied. If there is a use
|
||||
/// operand commutable with the tied use operand, find recurrence cycle
|
||||
@ -254,7 +259,7 @@ namespace {
|
||||
/// maintained with CommutePair.
|
||||
class RecurrenceInstr {
|
||||
public:
|
||||
typedef std::pair<unsigned, unsigned> IndexPair;
|
||||
using IndexPair = std::pair<unsigned, unsigned>;
|
||||
|
||||
RecurrenceInstr(MachineInstr *MI) : MI(MI) {}
|
||||
RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2)
|
||||
@ -277,11 +282,12 @@ namespace {
|
||||
SmallVector<TargetInstrInfo::RegSubRegPair, 2> RegSrcs;
|
||||
|
||||
/// Instruction using the sources in 'RegSrcs'.
|
||||
const MachineInstr *Inst;
|
||||
const MachineInstr *Inst = nullptr;
|
||||
|
||||
public:
|
||||
ValueTrackerResult() : Inst(nullptr) {}
|
||||
ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
|
||||
ValueTrackerResult() = default;
|
||||
|
||||
ValueTrackerResult(unsigned Reg, unsigned SubReg) {
|
||||
addSource(Reg, SubReg);
|
||||
}
|
||||
|
||||
@ -350,13 +356,17 @@ namespace {
|
||||
class ValueTracker {
|
||||
private:
|
||||
/// The current point into the use-def chain.
|
||||
const MachineInstr *Def;
|
||||
const MachineInstr *Def = nullptr;
|
||||
|
||||
/// The index of the definition in Def.
|
||||
unsigned DefIdx;
|
||||
unsigned DefIdx = 0;
|
||||
|
||||
/// The sub register index of the definition.
|
||||
unsigned DefSubReg;
|
||||
|
||||
/// The register where the value can be found.
|
||||
unsigned Reg;
|
||||
|
||||
/// Specifiy whether or not the value tracking looks through
|
||||
/// complex instructions. When this is false, the value tracker
|
||||
/// bails on everything that is not a copy or a bitcast.
|
||||
@ -365,8 +375,10 @@ namespace {
|
||||
/// the ValueTracker class but that would have complicated the code of
|
||||
/// the users of this class.
|
||||
bool UseAdvancedTracking;
|
||||
|
||||
/// MachineRegisterInfo used to perform tracking.
|
||||
const MachineRegisterInfo &MRI;
|
||||
|
||||
/// Optional TargetInstrInfo used to perform some complex
|
||||
/// tracking.
|
||||
const TargetInstrInfo *TII;
|
||||
@ -374,22 +386,29 @@ namespace {
|
||||
/// \brief Dispatcher to the right underlying implementation of
|
||||
/// getNextSource.
|
||||
ValueTrackerResult getNextSourceImpl();
|
||||
|
||||
/// \brief Specialized version of getNextSource for Copy instructions.
|
||||
ValueTrackerResult getNextSourceFromCopy();
|
||||
|
||||
/// \brief Specialized version of getNextSource for Bitcast instructions.
|
||||
ValueTrackerResult getNextSourceFromBitcast();
|
||||
|
||||
/// \brief Specialized version of getNextSource for RegSequence
|
||||
/// instructions.
|
||||
ValueTrackerResult getNextSourceFromRegSequence();
|
||||
|
||||
/// \brief Specialized version of getNextSource for InsertSubreg
|
||||
/// instructions.
|
||||
ValueTrackerResult getNextSourceFromInsertSubreg();
|
||||
|
||||
/// \brief Specialized version of getNextSource for ExtractSubreg
|
||||
/// instructions.
|
||||
ValueTrackerResult getNextSourceFromExtractSubreg();
|
||||
|
||||
/// \brief Specialized version of getNextSource for SubregToReg
|
||||
/// instructions.
|
||||
ValueTrackerResult getNextSourceFromSubregToReg();
|
||||
|
||||
/// \brief Specialized version of getNextSource for PHI instructions.
|
||||
ValueTrackerResult getNextSourceFromPHI();
|
||||
|
||||
@ -410,7 +429,7 @@ namespace {
|
||||
const MachineRegisterInfo &MRI,
|
||||
bool UseAdvancedTracking = false,
|
||||
const TargetInstrInfo *TII = nullptr)
|
||||
: Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
|
||||
: DefSubReg(DefSubReg), Reg(Reg),
|
||||
UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
|
||||
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
||||
Def = MRI.getVRegDef(Reg);
|
||||
@ -453,6 +472,7 @@ namespace {
|
||||
} // end anonymous namespace
|
||||
|
||||
char PeepholeOptimizer::ID = 0;
|
||||
|
||||
char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
|
||||
|
||||
INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE,
|
||||
@ -659,7 +679,7 @@ bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
|
||||
}
|
||||
|
||||
/// \brief Check if a simpler conditional branch can be
|
||||
// generated
|
||||
/// generated
|
||||
bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
|
||||
return TII->optimizeCondBranch(*MI);
|
||||
}
|
||||
@ -805,13 +825,13 @@ class CopyRewriter {
|
||||
protected:
|
||||
/// The copy-like instruction.
|
||||
MachineInstr &CopyLike;
|
||||
|
||||
/// The index of the source being rewritten.
|
||||
unsigned CurrentSrcIdx;
|
||||
unsigned CurrentSrcIdx = 0;
|
||||
|
||||
public:
|
||||
CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
|
||||
|
||||
virtual ~CopyRewriter() {}
|
||||
CopyRewriter(MachineInstr &MI) : CopyLike(MI) {}
|
||||
virtual ~CopyRewriter() = default;
|
||||
|
||||
/// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
|
||||
/// the related value that it affects (TrackReg, TrackSubReg).
|
||||
@ -944,6 +964,7 @@ class UncoalescableRewriter : public CopyRewriter {
|
||||
protected:
|
||||
const TargetInstrInfo &TII;
|
||||
MachineRegisterInfo &MRI;
|
||||
|
||||
/// The number of defs in the bitcast
|
||||
unsigned NumDefs;
|
||||
|
||||
@ -958,7 +979,6 @@ public:
|
||||
/// All such sources need to be considered rewritable in order to
|
||||
/// rewrite a uncoalescable copy-like instruction. This method return
|
||||
/// each definition that must be checked if rewritable.
|
||||
///
|
||||
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
||||
unsigned &TrackReg,
|
||||
unsigned &TrackSubReg) override {
|
||||
@ -1205,7 +1225,7 @@ public:
|
||||
}
|
||||
};
|
||||
|
||||
} // end anonymous namespace
|
||||
} // end anonymous namespace
|
||||
|
||||
/// \brief Get the appropriated CopyRewriter for \p MI.
|
||||
/// \return A pointer to a dynamically allocated CopyRewriter or nullptr
|
||||
@ -1847,7 +1867,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
||||
DEBUG(dbgs() << "Encountered load fold barrier on " << *MI << "\n");
|
||||
FoldAsLoadDefCandidates.clear();
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user