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[AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offset

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Before this, the LDS/STS instructions would have their opcodes
overwritten while linking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dylan McKay 2017-04-30 23:33:52 +00:00
parent 7c77a6cf1a
commit 900da3662a
5 changed files with 13 additions and 12 deletions
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10
lib/Target/AVR/AVRInstrInfo.td
View File

@ -183,33 +183,33 @@ def call_target : Operand<iPTR>
// A 16-bit address (which can lead to an R_AVR_16 relocation).
def imm16 : Operand<i16>
{
let EncoderMethod = "encodeImm<AVR::fixup_16>";
let EncoderMethod = "encodeImm<AVR::fixup_16, 2>";
}
/// A 6-bit immediate used in the ADIW/SBIW instructions.
def imm_arith6 : Operand<i16>
{
let EncoderMethod = "encodeImm<AVR::fixup_6_adiw>";
let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";
}
/// An 8-bit immediate inside an instruction with the same format
/// as the `LDI` instruction (the `FRdK` format).
def imm_ldi8 : Operand<i8>
{
let EncoderMethod = "encodeImm<AVR::fixup_ldi>";
let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";
}
/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).
def imm_port5 : Operand<i8>
{
let EncoderMethod = "encodeImm<AVR::fixup_port5>";
let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";
}
/// A 6-bit port number used in the `IN` instruction and friends (the
/// `FIORdA` format.
def imm_port6 : Operand<i8>
{
let EncoderMethod = "encodeImm<AVR::fixup_port6>";
let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";
}
// Addressing mode pattern reg+imm6

4
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
View File

@ -177,7 +177,7 @@ unsigned AVRMCCodeEmitter::encodeComplement(const MCInst &MI, unsigned OpNo,
return (~0) - Imm;
}
template <AVR::Fixups Fixup>
template <AVR::Fixups Fixup, unsigned Offset>
unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
@ -193,7 +193,7 @@ unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
}
MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind, MI.getLoc()));
Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), FixupKind, MI.getLoc()));
return 0;
}

3
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h
View File

@ -69,7 +69,8 @@ private:
const MCSubtargetInfo &STI) const;
/// Encodes an immediate value with a given fixup.
template <AVR::Fixups Fixup>
/// \tparam Offset The offset into the instruction for the fixup.
template <AVR::Fixups Fixup, unsigned Offset>
unsigned encodeImm(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

4
test/MC/AVR/inst-lds.s
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@ -12,5 +12,5 @@ foo:
; CHECK: lds r29, 190 ; encoding: [0xd0,0x91,0xbe,0x00]
; CHECK: lds r22, 172 ; encoding: [0x60,0x91,0xac,0x00]
; CHECK: lds r27, 92 ; encoding: [0xb0,0x91,0x5c,0x00]
; CHECK: lds r4, SYMBOL+12 ; encoding: [0x40'A',0x90'A',0x00,0x00]
; CHECK: ; fixup A - offset: 0, value: SYMBOL+12, kind: fixup_16
; CHECK: lds r4, SYMBOL+12 ; encoding: [0x40,0x90,A,A]
; CHECK: ; fixup A - offset: 2, value: SYMBOL+12, kind: fixup_16

4
test/MC/AVR/inst-sts.s
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@ -9,6 +9,6 @@ foo:
; CHECK: sts 3, r5 ; encoding: [0x50,0x92,0x03,0x00]
; CHECK: sts 255, r7 ; encoding: [0x70,0x92,0xff,0x00]
; CHECK: sts SYMBOL+1, r25 ; encoding: [0x90'A',0x93'A',0x00,0x00]
; CHECK: ; fixup A - offset: 0, value: SYMBOL+1, kind: fixup_16
; CHECK: sts SYMBOL+1, r25 ; encoding: [0x90,0x93,A,A]
; CHECK: ; fixup A - offset: 2, value: SYMBOL+1, kind: fixup_16