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On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of
its result if the condition is false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81814 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -387,13 +387,15 @@ def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
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[(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
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// Any instruction that defines a 32-bit result leaves the high half of the
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// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
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// be copying from a truncate, but any other 32-bit operation will zero-extend
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// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
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// be copying from a truncate. And x86's cmov doesn't do anything if the
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// condition is false. But any other 32-bit operation will zero-extend
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// up to 64 bits.
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def def32 : PatLeaf<(i32 GR32:$src), [{
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return N->getOpcode() != ISD::TRUNCATE &&
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N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
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N->getOpcode() != ISD::CopyFromReg;
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N->getOpcode() != ISD::CopyFromReg &&
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N->getOpcode() != X86ISD::CMOV;
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}]>;
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// In the case of a 32-bit def that is known to implicitly zero-extend,
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19
test/CodeGen/X86/cmov-zext.ll
Normal file
19
test/CodeGen/X86/cmov-zext.ll
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@ -0,0 +1,19 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination
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; if the condition is false. An explicit zero-extend (movl) is needed
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; after the cmov.
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; CHECK: cmovne %edi, %esi
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; CHECK-NEXT: movl %esi, %edi
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declare void @bar(i64) nounwind
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define void @foo(i64 %a, i64 %b, i1 %p) nounwind {
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%c = trunc i64 %a to i32
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%d = trunc i64 %b to i32
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%e = select i1 %p, i32 %c, i32 %d
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%f = zext i32 %e to i64
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call void @bar(i64 %f)
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ret void
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}
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