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t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-19 07:28:01 +00:00
parent 27fa722311
commit 9085f98b32
3 changed files with 41 additions and 6 deletions
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1
lib/Target/ARM/ARMInstrThumb.td
View File

@ -889,6 +889,7 @@ def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p\t$dst, #$label", []>,
T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10

1
lib/Target/ARM/ARMInstrThumb2.td
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@ -778,6 +778,7 @@ multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p.w\t$dst, #$label", []> {
let Inst{31-27} = 0b11110;

45
test/CodeGen/Thumb2/machine-licm.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
; rdar://7353541
; rdar://7354376
@ -8,9 +8,9 @@
@GV = external global i32 ; <i32*> [#uses=2]
define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind {
define arm_apcscc void @t1(i32* nocapture %vals, i32 %c) nounwind {
entry:
; CHECK: t:
; CHECK: t1:
; CHECK: cbz
%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
@ -22,8 +22,7 @@ bb.nph: ; preds = %entry
; CHECK: ldr r3, [r2]
; CHECK: LBB0_2
; CHECK: LCPI0_0:
; CHECK-NOT: LCPI1_1:
; CHECK: .section
; CHECK-NOT: LCPI0_1:
; PIC: BB#1
; PIC: ldr.n r2, LCPI0_0
@ -51,3 +50,37 @@ bb: ; preds = %bb, %bb.nph
return: ; preds = %bb, %entry
ret void
}
; rdar://8001136
define arm_apcscc void @t2(i8* %ptr1, i8* %ptr2) nounwind {
entry:
; CHECK: t2:
; CHECK: adr r{{.}}, #LCPI1_0
; CHECK: vldmia r3, {d0,d1}
br i1 undef, label %bb1, label %bb2
bb1:
; CHECK-NEXT: %bb1
%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
%tmp1 = shl i32 %indvar, 2
%gep1 = getelementptr i8* %ptr1, i32 %tmp1
%tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1)
%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
%gep2 = getelementptr i8* %ptr2, i32 %tmp1
call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3)
%indvar.next = add i32 %indvar, 1
%cond = icmp eq i32 %indvar.next, 10
br i1 %cond, label %bb2, label %bb1
bb2:
ret void
}
; CHECK: LCPI1_0:
; CHECK: .section
declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind
declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone