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AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.

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I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-24 12:42:26 +00:00
parent 4ca8b0b66d
commit 9105f66d6f
355 changed files with 73 additions and 67373 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
CMakeLists.txt
View File

@ -127,7 +127,6 @@ set(LLVM_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/include)
set(LLVM_LIBDIR_SUFFIX "" CACHE STRING "Define suffix of library directory name (32/64)" )
set(LLVM_ALL_TARGETS
AArch64
ARM64
ARM
CppBackend
@ -144,7 +143,7 @@ set(LLVM_ALL_TARGETS
)
# List of targets with JIT support:
set(LLVM_TARGETS_WITH_JIT X86 PowerPC AArch64 ARM64 ARM Mips SystemZ)
set(LLVM_TARGETS_WITH_JIT X86 PowerPC ARM64 ARM Mips SystemZ)
set(LLVM_TARGETS_TO_BUILD "all"
CACHE STRING "Semicolon-separated list of targets to build, or \"all\".")

13
autoconf/configure.ac
View File

@ -421,7 +421,7 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
arm64*-*) llvm_cv_target_arch="ARM64" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
aarch64*-*) llvm_cv_target_arch="AArch64" ;;
aarch64*-*) llvm_cv_target_arch="ARM64" ;;
mips-* | mips64-*) llvm_cv_target_arch="Mips" ;;
mipsel-* | mips64el-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@ -457,7 +457,7 @@ case $host in
powerpc*-*) host_arch="PowerPC" ;;
arm64*-*) host_arch="ARM64" ;;
arm*-*) host_arch="ARM" ;;
aarch64*-*) host_arch="AArch64" ;;
aarch64*-*) host_arch="ARM64" ;;
mips-* | mips64-*) host_arch="Mips" ;;
mipsel-* | mips64el-*) host_arch="Mips" ;;
xcore-*) host_arch="XCore" ;;
@ -786,7 +786,6 @@ else
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
AArch64) AC_SUBST(TARGET_HAS_JIT,0) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
MSP430) AC_SUBST(TARGET_HAS_JIT,0) ;;
@ -797,7 +796,7 @@ else
esac
fi
TARGETS_WITH_JIT="AArch64 ARM ARM64 Mips PowerPC SystemZ X86"
TARGETS_WITH_JIT="ARM ARM64 Mips PowerPC SystemZ X86"
AC_SUBST(TARGETS_WITH_JIT,$TARGETS_WITH_JIT)
dnl Allow enablement of building and installing docs
@ -950,7 +949,7 @@ if test "$llvm_cv_enable_crash_overrides" = "yes" ; then
fi
dnl List all possible targets
ALL_TARGETS="X86 Sparc PowerPC AArch64 ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
ALL_TARGETS="X86 Sparc PowerPC ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
AC_SUBST(ALL_TARGETS,$ALL_TARGETS)
dnl Allow specific targets to be specified for building (or not)
@ -971,7 +970,7 @@ case "$enableval" in
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
aarch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
aarch64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
arm64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
@ -990,7 +989,7 @@ case "$enableval" in
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
AArch64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;

14
configure vendored
View File

@ -4153,7 +4153,7 @@ else
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
arm64*-*) llvm_cv_target_arch="ARM64" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
aarch64*-*) llvm_cv_target_arch="AArch64" ;;
aarch64*-*) llvm_cv_target_arch="ARM64" ;;
mips-* | mips64-*) llvm_cv_target_arch="Mips" ;;
mipsel-* | mips64el-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@ -4190,7 +4190,7 @@ case $host in
powerpc*-*) host_arch="PowerPC" ;;
arm64*-*) host_arch="ARM64" ;;
arm*-*) host_arch="ARM" ;;
aarch64*-*) host_arch="AArch64" ;;
aarch64*-*) host_arch="ARM64" ;;
mips-* | mips64-*) host_arch="Mips" ;;
mipsel-* | mips64el-*) host_arch="Mips" ;;
xcore-*) host_arch="XCore" ;;
@ -5102,8 +5102,6 @@ else
x86_64) TARGET_HAS_JIT=1
;;
ARM) TARGET_HAS_JIT=1
;;
AArch64) TARGET_HAS_JIT=0
;;
Mips) TARGET_HAS_JIT=1
;;
@ -5122,7 +5120,7 @@ else
esac
fi
TARGETS_WITH_JIT="AArch64 ARM ARM64 Mips PowerPC SystemZ X86"
TARGETS_WITH_JIT="ARM ARM64 Mips PowerPC SystemZ X86"
TARGETS_WITH_JIT=$TARGETS_WITH_JIT
@ -5359,7 +5357,7 @@ _ACEOF
fi
ALL_TARGETS="X86 Sparc PowerPC AArch64 ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
ALL_TARGETS="X86 Sparc PowerPC ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600"
ALL_TARGETS=$ALL_TARGETS
@ -5382,7 +5380,7 @@ case "$enableval" in
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
aarch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
aarch64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
arm64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
@ -5401,7 +5399,7 @@ case "$enableval" in
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;;
AArch64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;

1
include/llvm/IR/Intrinsics.td
View File

@ -534,7 +534,6 @@ include "llvm/IR/IntrinsicsPowerPC.td"
include "llvm/IR/IntrinsicsX86.td"
include "llvm/IR/IntrinsicsARM.td"
include "llvm/IR/IntrinsicsARM64.td"
include "llvm/IR/IntrinsicsAArch64.td"
include "llvm/IR/IntrinsicsXCore.td"
include "llvm/IR/IntrinsicsHexagon.td"
include "llvm/IR/IntrinsicsNVVM.td"

407
include/llvm/IR/IntrinsicsAArch64.td
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@ -1,407 +0,0 @@
//===- IntrinsicsAArch64.td - Defines AArch64 intrinsics -----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines all of the AArch64-specific intrinsics.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Advanced SIMD (NEON)
let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
// Vector Absolute Compare (Floating Point)
def int_aarch64_neon_vacgeq :
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
def int_aarch64_neon_vacgtq :
Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
// Vector saturating accumulate
def int_aarch64_neon_suqadd : Neon_2Arg_Intrinsic;
def int_aarch64_neon_usqadd : Neon_2Arg_Intrinsic;
// Vector Bitwise reverse
def int_aarch64_neon_rbit : Neon_1Arg_Intrinsic;
// Vector extract and narrow
def int_aarch64_neon_xtn :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Vector floating-point convert
def int_aarch64_neon_frintn : Neon_1Arg_Intrinsic;
def int_aarch64_neon_fsqrt : Neon_1Arg_Intrinsic;
def int_aarch64_neon_vcvtxn :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
def int_aarch64_neon_vcvtzs :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
def int_aarch64_neon_vcvtzu :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Vector maxNum (Floating Point)
def int_aarch64_neon_vmaxnm : Neon_2Arg_Intrinsic;
// Vector minNum (Floating Point)
def int_aarch64_neon_vminnm : Neon_2Arg_Intrinsic;
// Vector Pairwise maxNum (Floating Point)
def int_aarch64_neon_vpmaxnm : Neon_2Arg_Intrinsic;
// Vector Pairwise minNum (Floating Point)
def int_aarch64_neon_vpminnm : Neon_2Arg_Intrinsic;
// Vector Multiply Extended and Scalar Multiply Extended (Floating Point)
def int_aarch64_neon_vmulx :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>;
class Neon_N2V_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty],
[IntrNoMem]>;
class Neon_N3V_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
[IntrNoMem]>;
class Neon_N2V_Narrow_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMExtendedType<0>, llvm_i32_ty],
[IntrNoMem]>;
// Vector rounding shift right by immediate (Signed)
def int_aarch64_neon_vsrshr : Neon_N2V_Intrinsic;
def int_aarch64_neon_vurshr : Neon_N2V_Intrinsic;
def int_aarch64_neon_vsqshlu : Neon_N2V_Intrinsic;
def int_aarch64_neon_vsri : Neon_N3V_Intrinsic;
def int_aarch64_neon_vsli : Neon_N3V_Intrinsic;
def int_aarch64_neon_vsqshrun : Neon_N2V_Narrow_Intrinsic;
def int_aarch64_neon_vrshrn : Neon_N2V_Narrow_Intrinsic;
def int_aarch64_neon_vsqrshrun : Neon_N2V_Narrow_Intrinsic;
def int_aarch64_neon_vsqshrn : Neon_N2V_Narrow_Intrinsic;
def int_aarch64_neon_vuqshrn : Neon_N2V_Narrow_Intrinsic;
def int_aarch64_neon_vsqrshrn : Neon_N2V_Narrow_Intrinsic;
def int_aarch64_neon_vuqrshrn : Neon_N2V_Narrow_Intrinsic;
// Vector across
class Neon_Across_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
def int_aarch64_neon_saddlv : Neon_Across_Intrinsic;
def int_aarch64_neon_uaddlv : Neon_Across_Intrinsic;
def int_aarch64_neon_smaxv : Neon_Across_Intrinsic;
def int_aarch64_neon_umaxv : Neon_Across_Intrinsic;
def int_aarch64_neon_sminv : Neon_Across_Intrinsic;
def int_aarch64_neon_uminv : Neon_Across_Intrinsic;
def int_aarch64_neon_vaddv : Neon_Across_Intrinsic;
def int_aarch64_neon_vmaxv :
Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_aarch64_neon_vminv :
Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_aarch64_neon_vmaxnmv :
Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
def int_aarch64_neon_vminnmv :
Intrinsic<[llvm_float_ty], [llvm_v4f32_ty], [IntrNoMem]>;
// Vector Table Lookup.
def int_aarch64_neon_vtbl1 :
Intrinsic<[llvm_anyvector_ty],
[llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_neon_vtbl2 :
Intrinsic<[llvm_anyvector_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
[IntrNoMem]>;
def int_aarch64_neon_vtbl3 :
Intrinsic<[llvm_anyvector_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_neon_vtbl4 :
Intrinsic<[llvm_anyvector_ty],
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
// Vector Table Extension.
// Some elements of the destination vector may not be updated, so the original
// value of that vector is passed as the first argument. The next 1-4
// arguments after that are the table.
def int_aarch64_neon_vtbx1 :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
[IntrNoMem]>;
def int_aarch64_neon_vtbx2 :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_neon_vtbx3 :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
def int_aarch64_neon_vtbx4 :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
[IntrNoMem]>;
// Vector Load/store
def int_aarch64_neon_vld1x2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_aarch64_neon_vld1x3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_aarch64_neon_vld1x4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_aarch64_neon_vst1x2 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, llvm_i32_ty],
[IntrReadWriteArgMem]>;
def int_aarch64_neon_vst1x3 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_aarch64_neon_vst1x4 : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty],
[IntrReadWriteArgMem]>;
// Scalar Add
def int_aarch64_neon_vaddds :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
def int_aarch64_neon_vadddu :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
// Scalar Sub
def int_aarch64_neon_vsubds :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
def int_aarch64_neon_vsubdu :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
// Scalar Shift
// Scalar Shift Left
def int_aarch64_neon_vshlds :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
def int_aarch64_neon_vshldu :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
// Scalar Saturating Shift Left
def int_aarch64_neon_vqshls : Neon_2Arg_Intrinsic;
def int_aarch64_neon_vqshlu : Neon_2Arg_Intrinsic;
// Scalar Shift Rouding Left
def int_aarch64_neon_vrshlds :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
def int_aarch64_neon_vrshldu :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
// Scalar Saturating Rounding Shift Left
def int_aarch64_neon_vqrshls : Neon_2Arg_Intrinsic;
def int_aarch64_neon_vqrshlu : Neon_2Arg_Intrinsic;
// Scalar Reduce Pairwise Add.
def int_aarch64_neon_vpadd :
Intrinsic<[llvm_v1i64_ty], [llvm_v2i64_ty],[IntrNoMem]>;
def int_aarch64_neon_vpfadd :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Scalar Reduce Pairwise Floating Point Max/Min.
def int_aarch64_neon_vpmax :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
def int_aarch64_neon_vpmin :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Scalar Reduce Pairwise Floating Point Maxnm/Minnm.
def int_aarch64_neon_vpfmaxnm :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
def int_aarch64_neon_vpfminnm :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Scalar Signed Integer Convert To Floating-point
def int_aarch64_neon_vcvtint2fps :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Scalar Unsigned Integer Convert To Floating-point
def int_aarch64_neon_vcvtint2fpu :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
// Scalar Floating-point Convert
def int_aarch64_neon_fcvtxn :
Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtns :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtnu :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtps :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtpu :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtms :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtmu :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtas :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtau :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtzs :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
def int_aarch64_neon_fcvtzu :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
// Scalar Floating-point Reciprocal Estimate.
def int_aarch64_neon_vrecpe :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
// Scalar Floating-point Reciprocal Exponent
def int_aarch64_neon_vrecpx :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
// Scalar Floating-point Reciprocal Square Root Estimate
def int_aarch64_neon_vrsqrte :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
// Scalar Floating-point Reciprocal Step
def int_aarch64_neon_vrecps :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
// Scalar Floating-point Reciprocal Square Root Step
def int_aarch64_neon_vrsqrts :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
// Compare with vector operands.
class Neon_Cmp_Intrinsic :
Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_anyvector_ty],
[IntrNoMem]>;
// Floating-point compare with scalar operands.
class Neon_Float_Cmp_Intrinsic :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_anyfloat_ty],
[IntrNoMem]>;
// Scalar Compare Equal
def int_aarch64_neon_vceq : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fceq : Neon_Float_Cmp_Intrinsic;
// Scalar Compare Greater-Than or Equal
def int_aarch64_neon_vcge : Neon_Cmp_Intrinsic;
def int_aarch64_neon_vchs : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fcge : Neon_Float_Cmp_Intrinsic;
def int_aarch64_neon_fchs : Neon_Float_Cmp_Intrinsic;
// Scalar Compare Less-Than or Equal
def int_aarch64_neon_vclez : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fclez : Neon_Float_Cmp_Intrinsic;
// Scalar Compare Less-Than
def int_aarch64_neon_vcltz : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fcltz : Neon_Float_Cmp_Intrinsic;
// Scalar Compare Greater-Than
def int_aarch64_neon_vcgt : Neon_Cmp_Intrinsic;
def int_aarch64_neon_vchi : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fcgt : Neon_Float_Cmp_Intrinsic;
def int_aarch64_neon_fchi : Neon_Float_Cmp_Intrinsic;
// Scalar Compare Bitwise Test Bits
def int_aarch64_neon_vtstd : Neon_Cmp_Intrinsic;
// Scalar Floating-point Absolute Compare Greater Than Or Equal
def int_aarch64_neon_vcage : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fcage : Neon_Float_Cmp_Intrinsic;
// Scalar Floating-point Absolute Compare Greater Than
def int_aarch64_neon_vcagt : Neon_Cmp_Intrinsic;
def int_aarch64_neon_fcagt : Neon_Float_Cmp_Intrinsic;
// Scalar Signed Saturating Accumulated of Unsigned Value
def int_aarch64_neon_vuqadd : Neon_2Arg_Intrinsic;
// Scalar Unsigned Saturating Accumulated of Signed Value
def int_aarch64_neon_vsqadd : Neon_2Arg_Intrinsic;
// Scalar Absolute Value
def int_aarch64_neon_vabs :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
// Scalar Absolute Difference
def int_aarch64_neon_vabd :
Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
// Scalar Negate Value
def int_aarch64_neon_vneg :
Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
// Signed Saturating Doubling Multiply-Add Long
def int_aarch64_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
// Signed Saturating Doubling Multiply-Subtract Long
def int_aarch64_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
def int_aarch64_neon_vmull_p64 :
Intrinsic<[llvm_v16i8_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
class Neon_2Arg_ShiftImm_Intrinsic
: Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
class Neon_3Arg_ShiftImm_Intrinsic
: Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty, llvm_i32_ty],
[IntrNoMem]>;
// Scalar Shift Right (Immediate)
def int_aarch64_neon_vshrds_n : Neon_2Arg_ShiftImm_Intrinsic;
def int_aarch64_neon_vshrdu_n : Neon_2Arg_ShiftImm_Intrinsic;
// Scalar Shift Right and Accumulate (Immediate)
def int_aarch64_neon_vsrads_n : Neon_3Arg_ShiftImm_Intrinsic;
def int_aarch64_neon_vsradu_n : Neon_3Arg_ShiftImm_Intrinsic;
// Scalar Rounding Shift Right and Accumulate (Immediate)
def int_aarch64_neon_vrsrads_n : Neon_3Arg_ShiftImm_Intrinsic;
def int_aarch64_neon_vrsradu_n : Neon_3Arg_ShiftImm_Intrinsic;
// Scalar Shift Left (Immediate)
def int_aarch64_neon_vshld_n : Neon_2Arg_ShiftImm_Intrinsic;
// Scalar Saturating Shift Left (Immediate)
def int_aarch64_neon_vqshls_n : Neon_N2V_Intrinsic;
def int_aarch64_neon_vqshlu_n : Neon_N2V_Intrinsic;
// Scalar Signed Saturating Shift Left Unsigned (Immediate)
def int_aarch64_neon_vqshlus_n : Neon_N2V_Intrinsic;
// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
def int_aarch64_neon_vcvtfxs2fp_n :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>;
// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
def int_aarch64_neon_vcvtfxu2fp_n :
Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>;
// Scalar Floating-point Convert To Signed Fixed-point (Immediate)
def int_aarch64_neon_vcvtfp2fxs_n :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
def int_aarch64_neon_vcvtfp2fxu_n :
Intrinsic<[llvm_anyvector_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
}

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//==-- AArch64.h - Top-level interface for AArch64 representation -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
// AArch64 back-end.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64_H
#define LLVM_TARGET_AARCH64_H
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class AArch64AsmPrinter;
class FunctionPass;
class AArch64TargetMachine;
class MachineInstr;
class MCInst;
FunctionPass *createAArch64ISelDAG(AArch64TargetMachine &TM,
CodeGenOpt::Level OptLevel);
FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
FunctionPass *createAArch64BranchFixupPass();
/// \brief Creates an AArch64-specific Target Transformation Info pass.
ImmutablePass *createAArch64TargetTransformInfoPass(
const AArch64TargetMachine *TM);
void LowerAArch64MachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AArch64AsmPrinter &AP);
}
#endif

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//===- AArch64.td - Describe the AArch64 Target Machine -------*- tblgen -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is the top level entry point for the AArch64 target.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// AArch64 Subtarget features.
//
def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
"Enable ARMv8 FP">;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable cryptographic instructions">;
//===----------------------------------------------------------------------===//
// AArch64 Processors
//
include "AArch64Schedule.td"
class ProcNoItin<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto]>;
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "AArch64RegisterInfo.td"
include "AArch64CallingConv.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "AArch64InstrInfo.td"
def AArch64InstrInfo : InstrInfo {
let noNamedPositionallyEncodedOperands = 1;
}
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def AArch64 : Target {
let InstructionSet = AArch64InstrInfo;
}

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//===-- AArch64AsmPrinter.cpp - Print machine code to an AArch64 .s file --===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
// of machine-dependent LLVM code to GAS-format AArch64 assembly language.
//
//===----------------------------------------------------------------------===//
#include "AArch64AsmPrinter.h"
#include "InstPrinter/AArch64InstPrinter.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
/// Try to print a floating-point register as if it belonged to a specified
/// register-class. For example the inline asm operand modifier "b" requires its
/// argument to be printed as "bN".
static bool printModifiedFPRAsmOperand(const MachineOperand &MO,
const TargetRegisterInfo *TRI,
char RegType, raw_ostream &O) {
if (!MO.isReg())
return true;
for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
if (AArch64::FPR8RegClass.contains(*AR)) {
O << RegType << TRI->getEncodingValue(MO.getReg());
return false;
}
}
// The register doesn't correspond to anything floating-point like.
return true;
}
/// Implements the 'w' and 'x' inline asm operand modifiers, which print a GPR
/// with the obvious type and an immediate 0 as either wzr or xzr.
static bool printModifiedGPRAsmOperand(const MachineOperand &MO,
const TargetRegisterInfo *TRI,
const TargetRegisterClass &RegClass,
raw_ostream &O) {
char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
if (MO.isImm() && MO.getImm() == 0) {
O << Prefix << "zr";
return false;
} else if (MO.isReg()) {
if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
O << (Prefix == 'x' ? "sp" : "wsp");
return false;
}
for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
if (RegClass.contains(*AR)) {
O << AArch64InstPrinter::getRegisterName(*AR);
return false;
}
}
}
return true;
}
bool AArch64AsmPrinter::printSymbolicAddress(const MachineOperand &MO,
bool PrintImmediatePrefix,
StringRef Suffix, raw_ostream &O) {
StringRef Name;
StringRef Modifier;
switch (MO.getType()) {
default:
return true;
case MachineOperand::MO_GlobalAddress:
Name = getSymbol(MO.getGlobal())->getName();
// Global variables may be accessed either via a GOT or in various fun and
// interesting TLS-model specific ways. Set the prefix modifier as
// appropriate here.
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal())) {
Reloc::Model RelocM = TM.getRelocationModel();
if (GV->isThreadLocal()) {
switch (TM.getTLSModel(GV)) {
case TLSModel::GeneralDynamic:
Modifier = "tlsdesc";
break;
case TLSModel::LocalDynamic:
Modifier = "dtprel";
break;
case TLSModel::InitialExec:
Modifier = "gottprel";
break;
case TLSModel::LocalExec:
Modifier = "tprel";
break;
}
} else if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
Modifier = "got";
}
}
break;
case MachineOperand::MO_BlockAddress:
Name = GetBlockAddressSymbol(MO.getBlockAddress())->getName();
break;
case MachineOperand::MO_ConstantPoolIndex:
Name = GetCPISymbol(MO.getIndex())->getName();
break;
}
// Some instructions (notably ADRP) don't take the # prefix for
// immediates. Only print it if asked to.
if (PrintImmediatePrefix)
O << '#';
// Only need the joining "_" if both the prefix and the suffix are
// non-null. This little block simply takes care of the four possibly
// combinations involved there.
if (Modifier == "" && Suffix == "")
O << Name;
else if (Modifier == "" && Suffix != "")
O << ":" << Suffix << ':' << Name;
else if (Modifier != "" && Suffix == "")
O << ":" << Modifier << ':' << Name;
else
O << ":" << Modifier << '_' << Suffix << ':' << Name;
return false;
}
bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O) {
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
if (!ExtraCode)
ExtraCode = "";
switch(ExtraCode[0]) {
default:
if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
return false;
break;
case 'w':
// Output 32-bit general register operand, constant zero as wzr, or stack
// pointer as wsp. Ignored when used with other operand types.
if (!printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
AArch64::GPR32RegClass, O))
return false;
break;
case 'x':
// Output 64-bit general register operand, constant zero as xzr, or stack
// pointer as sp. Ignored when used with other operand types.
if (!printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
AArch64::GPR64RegClass, O))
return false;
break;
case 'H':
// Output higher numbered of a 64-bit general register pair
case 'Q':
// Output least significant register of a 64-bit general register pair
case 'R':
// Output most significant register of a 64-bit general register pair
// FIXME note: these three operand modifiers will require, to some extent,
// adding a paired GPR64 register class. Initial investigation suggests that
// assertions are hit unless it has a type and is made legal for that type
// in ISelLowering. After that step is made, the number of modifications
// needed explodes (operation legality, calling conventions, stores, reg
// copies ...).
llvm_unreachable("FIXME: Unimplemented register pairs");
case 'b':
case 'h':
case 's':
case 'd':
case 'q':
if (!printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
ExtraCode[0], O))
return false;
break;
case 'A':
// Output symbolic address with appropriate relocation modifier (also
// suitable for ADRP).
if (!printSymbolicAddress(MI->getOperand(OpNum), false, "", O))
return false;
break;
case 'L':
// Output bits 11:0 of symbolic address with appropriate :lo12: relocation
// modifier.
if (!printSymbolicAddress(MI->getOperand(OpNum), true, "lo12", O))
return false;
break;
case 'G':
// Output bits 23:12 of symbolic address with appropriate :hi12: relocation
// modifier (currently only for TLS local exec).
if (!printSymbolicAddress(MI->getOperand(OpNum), true, "hi12", O))
return false;
break;
case 'a':
return PrintAsmMemoryOperand(MI, OpNum, AsmVariant, ExtraCode, O);
}
// There's actually no operand modifier, which leads to a slightly eclectic
// set of behaviour which we have to handle here.
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
default:
llvm_unreachable("Unexpected operand for inline assembly");
case MachineOperand::MO_Register:
// GCC prints the unmodified operand of a 'w' constraint as the vector
// register. Technically, we could allocate the argument as a VPR128, but
// that leads to extremely dodgy copies being generated to get the data
// there.
if (printModifiedFPRAsmOperand(MO, TRI, 'v', O))
O << AArch64InstPrinter::getRegisterName(MO.getReg());
break;
case MachineOperand::MO_Immediate:
O << '#' << MO.getImm();
break;
case MachineOperand::MO_FPImmediate:
assert(MO.getFPImm()->isExactlyValue(0.0) && "Only FP 0.0 expected");
O << "#0.0";
break;
case MachineOperand::MO_BlockAddress:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_GlobalAddress:
return printSymbolicAddress(MO, false, "", O);
}
return false;
}
bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNum,
unsigned AsmVariant,
const char *ExtraCode,
raw_ostream &O) {
// Currently both the memory constraints (m and Q) behave the same and amount
// to the address as a single register. In future, we may allow "m" to provide
// both a base and an offset.
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isReg() && "unexpected inline assembly memory operand");
O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']';
return false;
}
#include "AArch64GenMCPseudoLowering.inc"
void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Do any auto-generated pseudo lowerings.
if (emitPseudoExpansionLowering(OutStreamer, MI))
return;
MCInst TmpInst;
LowerAArch64MachineInstrToMCInst(MI, TmpInst, *this);
EmitToStreamer(OutStreamer, TmpInst);
}
void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
if (Subtarget->isTargetELF()) {
const TargetLoweringObjectFileELF &TLOFELF =
static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
// Output stubs for external and common global variables.
MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
if (!Stubs.empty()) {
OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
const DataLayout *TD = TM.getDataLayout();
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
OutStreamer.EmitLabel(Stubs[i].first);
OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
TD->getPointerSize(0));
}
Stubs.clear();
}
}
}
bool AArch64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
return AsmPrinter::runOnMachineFunction(MF);
}
// Force static initialization.
extern "C" void LLVMInitializeAArch64AsmPrinter() {
RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget);
RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget);
}

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// AArch64AsmPrinter.h - Print machine code to an AArch64 .s file -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the AArch64 assembly printer class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64ASMPRINTER_H
#define LLVM_AARCH64ASMPRINTER_H
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/Compiler.h"
namespace llvm {
class MCOperand;
class LLVM_LIBRARY_VISIBILITY AArch64AsmPrinter : public AsmPrinter {
/// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
/// make the right decision when printing asm code for different targets.
const AArch64Subtarget *Subtarget;
// emitPseudoExpansionLowering - tblgen'erated.
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
const MachineInstr *MI);
public:
explicit AArch64AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer) {
Subtarget = &TM.getSubtarget<AArch64Subtarget>();
}
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
MCOperand lowerSymbolOperand(const MachineOperand &MO,
const MCSymbol *Sym) const;
void EmitInstruction(const MachineInstr *MI) override;
void EmitEndOfAsmFile(Module &M) override;
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override;
/// printSymbolicAddress - Given some kind of reasonably bare symbolic
/// reference, print out the appropriate asm string to represent it. If
/// appropriate, a relocation-specifier will be produced, composed of a
/// general class derived from the MO parameter and an instruction-specific
/// suffix, provided in Suffix. E.g. ":got_lo12:" if a Suffix of "lo12" is
/// given.
bool printSymbolicAddress(const MachineOperand &MO,
bool PrintImmediatePrefix,
StringRef Suffix, raw_ostream &O);
const char *getPassName() const override {
return "AArch64 Assembly Printer";
}
bool runOnMachineFunction(MachineFunction &MF) override;
};
} // end namespace llvm
#endif

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//===-- AArch64BranchFixupPass.cpp - AArch64 branch fixup -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains a pass that fixes AArch64 branches which have ended up out
// of range for their immediate operands.
//
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "AArch64InstrInfo.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64-branch-fixup"
STATISTIC(NumSplit, "Number of uncond branches inserted");
STATISTIC(NumCBrFixed, "Number of cond branches fixed");
/// Return the worst case padding that could result from unknown offset bits.
/// This does not include alignment padding caused by known offset bits.
///
/// @param LogAlign log2(alignment)
/// @param KnownBits Number of known low offset bits.
static inline unsigned UnknownPadding(unsigned LogAlign, unsigned KnownBits) {
if (KnownBits < LogAlign)
return (1u << LogAlign) - (1u << KnownBits);
return 0;
}
namespace {
/// Due to limited PC-relative displacements, conditional branches to distant
/// blocks may need converting into an unconditional equivalent. For example:
/// tbz w1, #0, far_away
/// becomes
/// tbnz w1, #0, skip
/// b far_away
/// skip:
class AArch64BranchFixup : public MachineFunctionPass {
/// Information about the offset and size of a single basic block.
struct BasicBlockInfo {
/// Distance from the beginning of the function to the beginning of this
/// basic block.
///
/// Offsets are computed assuming worst case padding before an aligned
/// block. This means that subtracting basic block offsets always gives a
/// conservative estimate of the real distance which may be smaller.
///
/// Because worst case padding is used, the computed offset of an aligned
/// block may not actually be aligned.
unsigned Offset;
/// Size of the basic block in bytes. If the block contains inline
/// assembly, this is a worst case estimate.
///
/// The size does not include any alignment padding whether from the
/// beginning of the block, or from an aligned jump table at the end.
unsigned Size;
/// The number of low bits in Offset that are known to be exact. The
/// remaining bits of Offset are an upper bound.
uint8_t KnownBits;
/// When non-zero, the block contains instructions (inline asm) of unknown
/// size. The real size may be smaller than Size bytes by a multiple of 1
/// << Unalign.
uint8_t Unalign;
BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0) {}
/// Compute the number of known offset bits internally to this block.
/// This number should be used to predict worst case padding when
/// splitting the block.
unsigned internalKnownBits() const {
unsigned Bits = Unalign ? Unalign : KnownBits;
// If the block size isn't a multiple of the known bits, assume the
// worst case padding.
if (Size & ((1u << Bits) - 1))
Bits = countTrailingZeros(Size);
return Bits;
}
/// Compute the offset immediately following this block. If LogAlign is
/// specified, return the offset the successor block will get if it has
/// this alignment.
unsigned postOffset(unsigned LogAlign = 0) const {
unsigned PO = Offset + Size;
if (!LogAlign)
return PO;
// Add alignment padding from the terminator.
return PO + UnknownPadding(LogAlign, internalKnownBits());
}
/// Compute the number of known low bits of postOffset. If this block
/// contains inline asm, the number of known bits drops to the
/// instruction alignment. An aligned terminator may increase the number
/// of know bits.
/// If LogAlign is given, also consider the alignment of the next block.
unsigned postKnownBits(unsigned LogAlign = 0) const {
return std::max(LogAlign, internalKnownBits());
}
};
std::vector<BasicBlockInfo> BBInfo;
/// One per immediate branch, keeping the machine instruction pointer,
/// conditional or unconditional, the max displacement, and (if IsCond is
/// true) the corresponding inverted branch opcode.
struct ImmBranch {
MachineInstr *MI;
unsigned OffsetBits : 31;
bool IsCond : 1;
ImmBranch(MachineInstr *mi, unsigned offsetbits, bool cond)
: MI(mi), OffsetBits(offsetbits), IsCond(cond) {}
};
/// Keep track of all the immediate branch instructions.
///
std::vector<ImmBranch> ImmBranches;
MachineFunction *MF;
const AArch64InstrInfo *TII;
public:
static char ID;
AArch64BranchFixup() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const override {
return "AArch64 branch fixup pass";
}
private:
void initializeFunctionInfo();
MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
void adjustBBOffsetsAfter(MachineBasicBlock *BB);
bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB,
unsigned OffsetBits);
bool fixupImmediateBr(ImmBranch &Br);
bool fixupConditionalBr(ImmBranch &Br);
void computeBlockSize(MachineBasicBlock *MBB);
unsigned getOffsetOf(MachineInstr *MI) const;
void dumpBBs();
void verify();
};
char AArch64BranchFixup::ID = 0;
}
/// check BBOffsets
void AArch64BranchFixup::verify() {
#ifndef NDEBUG
for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
unsigned MBBId = MBB->getNumber();
assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
}
#endif
}
/// print block size and offset information - debugging
void AArch64BranchFixup::dumpBBs() {
DEBUG({
for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
const BasicBlockInfo &BBI = BBInfo[J];
dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
<< " kb=" << unsigned(BBI.KnownBits)
<< " ua=" << unsigned(BBI.Unalign)
<< format(" size=%#x\n", BBInfo[J].Size);
}
});
}
/// Returns an instance of the branch fixup pass.
FunctionPass *llvm::createAArch64BranchFixupPass() {
return new AArch64BranchFixup();
}
bool AArch64BranchFixup::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
DEBUG(dbgs() << "***** AArch64BranchFixup ******");
TII = (const AArch64InstrInfo*)MF->getTarget().getInstrInfo();
// This pass invalidates liveness information when it splits basic blocks.
MF->getRegInfo().invalidateLiveness();
// Renumber all of the machine basic blocks in the function, guaranteeing that
// the numbers agree with the position of the block in the function.
MF->RenumberBlocks();
// Do the initial scan of the function, building up information about the
// sizes of each block and location of each immediate branch.
initializeFunctionInfo();
// Iteratively fix up branches until there is no change.
unsigned NoBRIters = 0;
bool MadeChange = false;
while (true) {
DEBUG(dbgs() << "Beginning iteration #" << NoBRIters << '\n');
bool BRChange = false;
for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
BRChange |= fixupImmediateBr(ImmBranches[i]);
if (BRChange && ++NoBRIters > 30)
report_fatal_error("Branch Fix Up pass failed to converge!");
DEBUG(dumpBBs());
if (!BRChange)
break;
MadeChange = true;
}
// After a while, this might be made debug-only, but it is not expensive.
verify();
DEBUG(dbgs() << '\n'; dumpBBs());
BBInfo.clear();
ImmBranches.clear();
return MadeChange;
}
/// Return true if the specified basic block can fallthrough into the block
/// immediately after it.
static bool BBHasFallthrough(MachineBasicBlock *MBB) {
// Get the next machine basic block in the function.
MachineFunction::iterator MBBI = MBB;
// Can't fall off end of function.
if (std::next(MBBI) == MBB->getParent()->end())
return false;
MachineBasicBlock *NextBB = std::next(MBBI);
for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
E = MBB->succ_end(); I != E; ++I)
if (*I == NextBB)
return true;
return false;
}
/// Do the initial scan of the function, building up information about the sizes
/// of each block, and each immediate branch.
void AArch64BranchFixup::initializeFunctionInfo() {
BBInfo.clear();
BBInfo.resize(MF->getNumBlockIDs());
// First thing, compute the size of all basic blocks, and see if the function
// has any inline assembly in it. If so, we have to be conservative about
// alignment assumptions, as we don't know for sure the size of any
// instructions in the inline assembly.
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
computeBlockSize(I);
// The known bits of the entry block offset are determined by the function
// alignment.
BBInfo.front().KnownBits = MF->getAlignment();
// Compute block offsets and known bits.
adjustBBOffsetsAfter(MF->begin());
// Now go back through the instructions and build up our data structures.
for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
MBBI != E; ++MBBI) {
MachineBasicBlock &MBB = *MBBI;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
if (I->isDebugValue())
continue;
int Opc = I->getOpcode();
if (I->isBranch()) {
bool IsCond = false;
// The offsets encoded in instructions here scale by the instruction
// size (4 bytes), effectively increasing their range by 2 bits.
unsigned Bits = 0;
switch (Opc) {
default:
continue; // Ignore other JT branches
case AArch64::TBZxii:
case AArch64::TBZwii:
case AArch64::TBNZxii:
case AArch64::TBNZwii:
IsCond = true;
Bits = 14 + 2;
break;
case AArch64::Bcc:
case AArch64::CBZx:
case AArch64::CBZw:
case AArch64::CBNZx:
case AArch64::CBNZw:
IsCond = true;
Bits = 19 + 2;
break;
case AArch64::Bimm:
Bits = 26 + 2;
break;
}
// Record this immediate branch.
ImmBranches.push_back(ImmBranch(I, Bits, IsCond));
}
}
}
}
/// Compute the size and some alignment information for MBB. This function
/// updates BBInfo directly.
void AArch64BranchFixup::computeBlockSize(MachineBasicBlock *MBB) {
BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
BBI.Size = 0;
BBI.Unalign = 0;
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
++I) {
BBI.Size += TII->getInstSizeInBytes(*I);
// For inline asm, GetInstSizeInBytes returns a conservative estimate.
// The actual size may be smaller, but still a multiple of the instr size.
if (I->isInlineAsm())
BBI.Unalign = 2;
}
}
/// Return the current offset of the specified machine instruction from the
/// start of the function. This offset changes as stuff is moved around inside
/// the function.
unsigned AArch64BranchFixup::getOffsetOf(MachineInstr *MI) const {
MachineBasicBlock *MBB = MI->getParent();
// The offset is composed of two things: the sum of the sizes of all MBB's
// before this instruction's block, and the offset from the start of the block
// it is in.
unsigned Offset = BBInfo[MBB->getNumber()].Offset;
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->getInstSizeInBytes(*I);
}
return Offset;
}
/// Split the basic block containing MI into two blocks, which are joined by
/// an unconditional branch. Update data structures and renumber blocks to
/// account for this change and returns the newly created block.
MachineBasicBlock *
AArch64BranchFixup::splitBlockBeforeInstr(MachineInstr *MI) {
MachineBasicBlock *OrigBB = MI->getParent();
// Create a new MBB for the code after the OrigBB.
MachineBasicBlock *NewBB =
MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
MachineFunction::iterator MBBI = OrigBB; ++MBBI;
MF->insert(MBBI, NewBB);
// Splice the instructions starting with MI over to NewBB.
NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
// Add an unconditional branch from OrigBB to NewBB.
// Note the new unconditional branch is not being recorded.
// There doesn't seem to be meaningful DebugInfo available; this doesn't
// correspond to anything in the source.
BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
++NumSplit;
// Update the CFG. All succs of OrigBB are now succs of NewBB.
NewBB->transferSuccessors(OrigBB);
// OrigBB branches to NewBB.
OrigBB->addSuccessor(NewBB);
// Update internal data structures to account for the newly inserted MBB.
MF->RenumberBlocks(NewBB);
// Insert an entry into BBInfo to align it properly with the (newly
// renumbered) block numbers.
BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
// Figure out how large the OrigBB is. As the first half of the original
// block, it cannot contain a tablejump. The size includes
// the new jump we added. (It should be possible to do this without
// recounting everything, but it's very confusing, and this is rarely
// executed.)
computeBlockSize(OrigBB);
// Figure out how large the NewMBB is. As the second half of the original
// block, it may contain a tablejump.
computeBlockSize(NewBB);
// All BBOffsets following these blocks must be modified.
adjustBBOffsetsAfter(OrigBB);
return NewBB;
}
void AArch64BranchFixup::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
unsigned BBNum = BB->getNumber();
for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
// Get the offset and known bits at the end of the layout predecessor.
// Include the alignment of the current block.
unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
// This is where block i begins. Stop if the offset is already correct,
// and we have updated 2 blocks. This is the maximum number of blocks
// changed before calling this function.
if (i > BBNum + 2 &&
BBInfo[i].Offset == Offset &&
BBInfo[i].KnownBits == KnownBits)
break;
BBInfo[i].Offset = Offset;
BBInfo[i].KnownBits = KnownBits;
}
}
/// Returns true if the distance between specific MI and specific BB can fit in
/// MI's displacement field.
bool AArch64BranchFixup::isBBInRange(MachineInstr *MI,
MachineBasicBlock *DestBB,
unsigned OffsetBits) {
int64_t BrOffset = getOffsetOf(MI);
int64_t DestOffset = BBInfo[DestBB->getNumber()].Offset;
DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
<< " from BB#" << MI->getParent()->getNumber()
<< " bits available=" << OffsetBits
<< " from " << getOffsetOf(MI) << " to " << DestOffset
<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
return isIntN(OffsetBits, DestOffset - BrOffset);
}
/// Fix up an immediate branch whose destination is too far away to fit in its
/// displacement field.
bool AArch64BranchFixup::fixupImmediateBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *DestBB = nullptr;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if (MI->getOperand(i).isMBB()) {
DestBB = MI->getOperand(i).getMBB();
break;
}
}
assert(DestBB && "Branch with no destination BB?");
// Check to see if the DestBB is already in-range.
if (isBBInRange(MI, DestBB, Br.OffsetBits))
return false;
assert(Br.IsCond && "Only conditional branches should need fixup");
return fixupConditionalBr(Br);
}
/// Fix up a conditional branch whose destination is too far away to fit in its
/// displacement field. It is converted to an inverse conditional branch + an
/// unconditional branch to the destination.
bool
AArch64BranchFixup::fixupConditionalBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *MBB = MI->getParent();
unsigned CondBrMBBOperand = 0;
// The general idea is to add an unconditional branch to the destination and
// invert the conditional branch to jump over it. Complications occur around
// fallthrough and unreachable ends to the block.
// b.lt L1
// =>
// b.ge L2
// b L1
// L2:
// First we invert the conditional branch, by creating a replacement if
// necessary. This if statement contains all the special handling of different
// branch types.
if (MI->getOpcode() == AArch64::Bcc) {
// The basic block is operand number 1 for Bcc
CondBrMBBOperand = 1;
A64CC::CondCodes CC = (A64CC::CondCodes)MI->getOperand(0).getImm();
CC = A64InvertCondCode(CC);
MI->getOperand(0).setImm(CC);
} else {
MachineInstrBuilder InvertedMI;
int InvertedOpcode;
switch (MI->getOpcode()) {
default: llvm_unreachable("Unknown branch type");
case AArch64::TBZxii: InvertedOpcode = AArch64::TBNZxii; break;
case AArch64::TBZwii: InvertedOpcode = AArch64::TBNZwii; break;
case AArch64::TBNZxii: InvertedOpcode = AArch64::TBZxii; break;
case AArch64::TBNZwii: InvertedOpcode = AArch64::TBZwii; break;
case AArch64::CBZx: InvertedOpcode = AArch64::CBNZx; break;
case AArch64::CBZw: InvertedOpcode = AArch64::CBNZw; break;
case AArch64::CBNZx: InvertedOpcode = AArch64::CBZx; break;
case AArch64::CBNZw: InvertedOpcode = AArch64::CBZw; break;
}
InvertedMI = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(InvertedOpcode));
for (unsigned i = 0, e= MI->getNumOperands(); i != e; ++i) {
InvertedMI.addOperand(MI->getOperand(i));
if (MI->getOperand(i).isMBB())
CondBrMBBOperand = i;
}
MI->eraseFromParent();
MI = Br.MI = InvertedMI;
}
// If the branch is at the end of its MBB and that has a fall-through block,
// direct the updated conditional branch to the fall-through
// block. Otherwise, split the MBB before the next instruction.
MachineInstr *BMI = &MBB->back();
bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
++NumCBrFixed;
if (BMI != MI) {
if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
BMI->getOpcode() == AArch64::Bimm) {
// Last MI in the BB is an unconditional branch. We can swap destinations:
// b.eq L1 (temporarily b.ne L1 after first change)
// b L2
// =>
// b.ne L2
// b L1
MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
if (isBBInRange(MI, NewDest, Br.OffsetBits)) {
DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
<< *BMI);
MachineBasicBlock *DestBB = MI->getOperand(CondBrMBBOperand).getMBB();
BMI->getOperand(0).setMBB(DestBB);
MI->getOperand(CondBrMBBOperand).setMBB(NewDest);
return true;
}
}
}
if (NeedSplit) {
MachineBasicBlock::iterator MBBI = MI; ++MBBI;
splitBlockBeforeInstr(MBBI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
int delta = TII->getInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
}
// After splitting and removing the unconditional branch from the original BB,
// the structure is now:
// oldbb:
// [things]
// b.invertedCC L1
// splitbb/fallthroughbb:
// [old b L2/real continuation]
//
// We now have to change the conditional branch to point to splitbb and add an
// unconditional branch after it to L1, giving the final structure:
// oldbb:
// [things]
// b.invertedCC splitbb
// b L1
// splitbb/fallthroughbb:
// [old b L2/real continuation]
MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
DEBUG(dbgs() << " Insert B to BB#"
<< MI->getOperand(CondBrMBBOperand).getMBB()->getNumber()
<< " also invert condition and change dest. to BB#"
<< NextBB->getNumber() << "\n");
// Insert a new unconditional branch and fixup the destination of the
// conditional one. Also update the ImmBranch as well as adding a new entry
// for the new branch.
BuildMI(MBB, DebugLoc(), TII->get(AArch64::Bimm))
.addMBB(MI->getOperand(CondBrMBBOperand).getMBB());
MI->getOperand(CondBrMBBOperand).setMBB(NextBB);
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
// 26 bits written down in Bimm, specifying a multiple of 4.
unsigned OffsetBits = 26 + 2;
ImmBranches.push_back(ImmBranch(&MBB->back(), OffsetBits, false));
adjustBBOffsetsAfter(MBB);
return true;
}

197
lib/Target/AArch64/AArch64CallingConv.td
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@ -1,197 +0,0 @@
//==-- AArch64CallingConv.td - Calling Conventions for ARM ----*- tblgen -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// This describes the calling conventions for AArch64 architecture.
//===----------------------------------------------------------------------===//
// The AArch64 Procedure Call Standard is unfortunately specified at a slightly
// higher level of abstraction than LLVM's target interface presents. In
// particular, it refers (like other ABIs, in fact) directly to
// structs. However, generic LLVM code takes the liberty of lowering structure
// arguments to the component fields before we see them.
//
// As a result, the obvious direct map from LLVM IR to PCS concepts can't be
// implemented, so the goals of this calling convention are, in decreasing
// priority order:
// 1. Expose *some* way to express the concepts required to implement the
// generic PCS from a front-end.
// 2. Provide a sane ABI for pure LLVM.
// 3. Follow the generic PCS as closely as is naturally possible.
//
// The suggested front-end implementation of PCS features is:
// * Integer, float and vector arguments of all sizes which end up in
// registers are passed and returned via the natural LLVM type.
// * Structure arguments with size <= 16 bytes are passed and returned in
// registers as similar integer or composite types. For example:
// [1 x i64], [2 x i64] or [1 x i128] (if alignment 16 needed).
// * HFAs in registers follow rules similar to small structs: appropriate
// composite types.
// * Structure arguments with size > 16 bytes are passed via a pointer,
// handled completely by the front-end.
// * Structure return values > 16 bytes via an sret pointer argument.
// * Other stack-based arguments (not large structs) are passed using byval
// pointers. Padding arguments are added beforehand to guarantee a large
// struct doesn't later use integer registers.
//
// N.b. this means that it is the front-end's responsibility (if it cares about
// PCS compliance) to check whether enough registers are available for an
// argument when deciding how to pass it.
class CCIfAlign<int Align, CCAction A>:
CCIf<"ArgFlags.getOrigAlign() == " # Align, A>;
def CC_A64_APCS : CallingConv<[
// SRet is an LLVM-specific concept, so it takes precedence over general ABI
// concerns. However, this rule will be used by C/C++ frontends to implement
// structure return.
CCIfSRet<CCAssignToReg<[X8]>>,
// Put ByVal arguments directly on the stack. Minimum size and alignment of a
// slot is 64-bit.
CCIfByVal<CCPassByVal<8, 8>>,
// Canonicalise the various types that live in different floating-point
// registers. This makes sense because the PCS does not distinguish Short
// Vectors and Floating-point types.
CCIfType<[v1i16, v2i8], CCBitConvertToType<f16>>,
CCIfType<[v1i32, v4i8, v2i16], CCBitConvertToType<f32>>,
CCIfType<[v8i8, v4i16, v2i32, v2f32, v1i64, v1f64], CCBitConvertToType<f64>>,
CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
CCBitConvertToType<f128>>,
// PCS: "C.1: If the argument is a Half-, Single-, Double- or Quad- precision
// Floating-point or Short Vector Type and the NSRN is less than 8, then the
// argument is allocated to the least significant bits of register
// v[NSRN]. The NSRN is incremented by one. The argument has now been
// allocated."
CCIfType<[v1i8], CCAssignToReg<[B0, B1, B2, B3, B4, B5, B6, B7]>>,
CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7]>>,
CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
CCIfType<[f128], CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
// PCS: "C.2: If the argument is an HFA and there are sufficient unallocated
// SIMD and Floating-point registers (NSRN - number of elements < 8), then the
// argument is allocated to SIMD and Floating-point registers (with one
// register per element of the HFA). The NSRN is incremented by the number of
// registers used. The argument has now been allocated."
//
// N.b. As above, this rule is the responsibility of the front-end.
// "C.3: If the argument is an HFA then the NSRN is set to 8 and the size of
// the argument is rounded up to the nearest multiple of 8 bytes."
//
// "C.4: If the argument is an HFA, a Quad-precision Floating-point or Short
// Vector Type then the NSAA is rounded up to the larger of 8 or the Natural
// Alignment of the Argument's type."
//
// It is expected that these will be satisfied by adding dummy arguments to
// the prototype.
// PCS: "C.5: If the argument is a Half- or Single- precision Floating-point
// type then the size of the argument is set to 8 bytes. The effect is as if
// the argument had been copied to the least significant bits of a 64-bit
// register and the remaining bits filled with unspecified values."
CCIfType<[f16, f32], CCPromoteToType<f64>>,
// PCS: "C.6: If the argument is an HFA, a Half-, Single-, Double- or Quad-
// precision Floating-point or Short Vector Type, then the argument is copied
// to memory at the adjusted NSAA. The NSAA is incremented by the size of the
// argument. The argument has now been allocated."
CCIfType<[f64], CCAssignToStack<8, 8>>,
CCIfType<[f128], CCAssignToStack<16, 16>>,
// PCS: "C.7: If the argument is an Integral Type, the size of the argument is
// less than or equal to 8 bytes and the NGRN is less than 8, the argument is
// copied to the least significant bits of x[NGRN]. The NGRN is incremented by
// one. The argument has now been allocated."
// First we implement C.8 and C.9 (128-bit types get even registers). i128 is
// represented as two i64s, the first one being split. If we delayed this
// operation C.8 would never be reached.
CCIfType<[i64],
CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6], [X0, X1, X3, X5]>>>,
// Note: the promotion also implements C.14.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// And now the real implementation of C.7
CCIfType<[i64], CCAssignToReg<[X0, X1, X2, X3, X4, X5, X6, X7]>>,
// PCS: "C.8: If the argument has an alignment of 16 then the NGRN is rounded
// up to the next even number."
//
// "C.9: If the argument is an Integral Type, the size of the argument is
// equal to 16 and the NGRN is less than 7, the argument is copied to x[NGRN]
// and x[NGRN+1], x[NGRN] shall contain the lower addressed double-word of the
// memory representation of the argument. The NGRN is incremented by two. The
// argument has now been allocated."
//
// Subtlety here: what if alignment is 16 but it is not an integral type? All
// floating-point types have been allocated already, which leaves composite
// types: this is why a front-end may need to produce i128 for a struct <= 16
// bytes.
// PCS: "C.10 If the argument is a Composite Type and the size in double-words
// of the argument is not more than 8 minus NGRN, then the argument is copied
// into consecutive general-purpose registers, starting at x[NGRN]. The
// argument is passed as though it had been loaded into the registers from a
// double-word aligned address with an appropriate sequence of LDR
// instructions loading consecutive registers from memory (the contents of any
// unused parts of the registers are unspecified by this standard). The NGRN
// is incremented by the number of registers used. The argument has now been
// allocated."
//
// Another one that's the responsibility of the front-end (sigh).
// PCS: "C.11: The NGRN is set to 8."
CCCustom<"CC_AArch64NoMoreRegs">,
// PCS: "C.12: The NSAA is rounded up to the larger of 8 or the Natural
// Alignment of the argument's type."
//
// PCS: "C.13: If the argument is a composite type then the argument is copied
// to memory at the adjusted NSAA. The NSAA is by the size of the
// argument. The argument has now been allocated."
//
// Note that the effect of this corresponds to a memcpy rather than register
// stores so that the struct ends up correctly addressable at the adjusted
// NSAA.
// PCS: "C.14: If the size of the argument is less than 8 bytes then the size
// of the argument is set to 8 bytes. The effect is as if the argument was
// copied to the least significant bits of a 64-bit register and the remaining
// bits filled with unspecified values."
//
// Integer types were widened above. Floating-point and composite types have
// already been allocated completely. Nothing to do.
// PCS: "C.15: The argument is copied to memory at the adjusted NSAA. The NSAA
// is incremented by the size of the argument. The argument has now been
// allocated."
CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
CCIfType<[i64], CCAssignToStack<8, 8>>
]>;
// According to the PCS, X19-X30 are callee-saved, however only the low 64-bits
// of vector registers (8-15) are callee-saved. The order here is is picked up
// by PrologEpilogInserter.cpp to allocate stack slots, starting from top of
// stack upon entry. This gives the customary layout of x30 at [sp-8], x29 at
// [sp-16], ...
def CSR_PCS : CalleeSavedRegs<(add (sequence "X%u", 30, 19),
(sequence "D%u", 15, 8))>;
// TLS descriptor calls are extremely restricted in their changes, to allow
// optimisations in the (hopefully) more common fast path where no real action
// is needed. They actually have to preserve all registers, except for the
// unavoidable X30 and the return register X0.
def TLSDesc : CalleeSavedRegs<(add (sequence "X%u", 29, 1),
(sequence "Q%u", 31, 0))>;

626
lib/Target/AArch64/AArch64FrameLowering.cpp
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@ -1,626 +0,0 @@
//===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "AArch64FrameLowering.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
void AArch64FrameLowering::splitSPAdjustments(uint64_t Total,
uint64_t &Initial,
uint64_t &Residual) const {
// 0x1f0 here is a pessimistic (i.e. realistic) boundary: x-register LDP
// instructions have a 7-bit signed immediate scaled by 8, giving a reach of
// 0x1f8, but stack adjustment should always be a multiple of 16.
if (Total <= 0x1f0) {
Initial = Total;
Residual = 0;
} else {
Initial = 0x1f0;
Residual = Total - Initial;
}
}
void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
AArch64MachineFunctionInfo *FuncInfo =
MF.getInfo<AArch64MachineFunctionInfo>();
MachineBasicBlock &MBB = MF.front();
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
bool NeedsFrameMoves = MMI.hasDebugInfo()
|| MF.getFunction()->needsUnwindTableEntry();
uint64_t NumInitialBytes, NumResidualBytes;
// Currently we expect the stack to be laid out by
// sub sp, sp, #initial
// stp x29, x30, [sp, #offset]
// ...
// str xxx, [sp, #offset]
// sub sp, sp, #rest (possibly via extra instructions).
if (MFI->getCalleeSavedInfo().size()) {
// If there are callee-saved registers, we want to store them efficiently as
// a block, and virtual base assignment happens too early to do it for us so
// we adjust the stack in two phases: first just for callee-saved fiddling,
// then to allocate the rest of the frame.
splitSPAdjustments(MFI->getStackSize(), NumInitialBytes, NumResidualBytes);
} else {
// If there aren't any callee-saved registers, two-phase adjustment is
// inefficient. It's more efficient to adjust with NumInitialBytes too
// because when we're in a "callee pops argument space" situation, that pop
// must be tacked onto Initial for correctness.
NumInitialBytes = MFI->getStackSize();
NumResidualBytes = 0;
}
// Tell everyone else how much adjustment we're expecting them to use. In
// particular if an adjustment is required for a tail call the epilogue could
// have a different view of things.
FuncInfo->setInitialStackAdjust(NumInitialBytes);
emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
MachineInstr::FrameSetup);
if (NeedsFrameMoves && NumInitialBytes) {
// We emit this update even if the CFA is set from a frame pointer later so
// that the CFA is valid in the interim.
MachineLocation Dst(MachineLocation::VirtualFP);
unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
unsigned CFIIndex = MMI.addFrameInst(
MCCFIInstruction::createDefCfa(nullptr, Reg, -NumInitialBytes));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
// Otherwise we need to set the frame pointer and/or add a second stack
// adjustment.
bool FPNeedsSetting = hasFP(MF);
for (; MBBI != MBB.end(); ++MBBI) {
// Note that this search makes strong assumptions about the operation used
// to store the frame-pointer: it must be "STP x29, x30, ...". This could
// change in future, but until then there's no point in implementing
// untestable more generic cases.
if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
&& MBBI->getOperand(0).getReg() == AArch64::X29) {
int64_t X29FrameIdx = MBBI->getOperand(2).getIndex();
FuncInfo->setFramePointerOffset(MFI->getObjectOffset(X29FrameIdx));
++MBBI;
emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
AArch64::X29,
NumInitialBytes + MFI->getObjectOffset(X29FrameIdx),
MachineInstr::FrameSetup);
// The offset adjustment used when emitting debugging locations relative
// to whatever frame base is set. AArch64 uses the default frame base (FP
// or SP) and this adjusts the calculations to be correct.
MFI->setOffsetAdjustment(- MFI->getObjectOffset(X29FrameIdx)
- MFI->getStackSize());
if (NeedsFrameMoves) {
unsigned Reg = MRI->getDwarfRegNum(AArch64::X29, true);
unsigned Offset = MFI->getObjectOffset(X29FrameIdx);
unsigned CFIIndex = MMI.addFrameInst(
MCCFIInstruction::createDefCfa(nullptr, Reg, Offset));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
FPNeedsSetting = false;
}
if (!MBBI->getFlag(MachineInstr::FrameSetup))
break;
}
assert(!FPNeedsSetting && "Frame pointer couldn't be set");
emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
MachineInstr::FrameSetup);
// Now we emit the rest of the frame setup information, if necessary: we've
// already noted the FP and initial SP moves so we're left with the prologue's
// final SP update and callee-saved register locations.
if (!NeedsFrameMoves)
return;
// The rest of the stack adjustment
if (!hasFP(MF) && NumResidualBytes) {
MachineLocation Dst(MachineLocation::VirtualFP);
unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
unsigned Offset = NumResidualBytes + NumInitialBytes;
unsigned CFIIndex =
MMI.addFrameInst(MCCFIInstruction::createDefCfa(nullptr, Reg, -Offset));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
// And any callee-saved registers (it's fine to leave them to the end here,
// because the old values are still valid at this point.
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
if (CSI.size()) {
for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
E = CSI.end(); I != E; ++I) {
unsigned Offset = MFI->getObjectOffset(I->getFrameIdx());
unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
unsigned CFIIndex = MMI.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, Offset));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex);
}
}
}
void
AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
AArch64MachineFunctionInfo *FuncInfo =
MF.getInfo<AArch64MachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
DebugLoc DL = MBBI->getDebugLoc();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned RetOpcode = MBBI->getOpcode();
// Initial and residual are named for consitency with the prologue. Note that
// in the epilogue, the residual adjustment is executed first.
uint64_t NumInitialBytes = FuncInfo->getInitialStackAdjust();
uint64_t NumResidualBytes = MFI.getStackSize() - NumInitialBytes;
uint64_t ArgumentPopSize = 0;
if (RetOpcode == AArch64::TC_RETURNdi ||
RetOpcode == AArch64::TC_RETURNxi) {
MachineOperand &JumpTarget = MBBI->getOperand(0);
MachineOperand &StackAdjust = MBBI->getOperand(1);
MachineInstrBuilder MIB;
if (RetOpcode == AArch64::TC_RETURNdi) {
MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
if (JumpTarget.isGlobal()) {
MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
JumpTarget.getTargetFlags());
} else {
assert(JumpTarget.isSymbol() && "unexpected tail call destination");
MIB.addExternalSymbol(JumpTarget.getSymbolName(),
JumpTarget.getTargetFlags());
}
} else {
assert(RetOpcode == AArch64::TC_RETURNxi && JumpTarget.isReg()
&& "Unexpected tail call");
MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
MIB.addReg(JumpTarget.getReg(), RegState::Kill);
}
// Add the extra operands onto the new tail call instruction even though
// they're not used directly (so that liveness is tracked properly etc).
for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
MIB->addOperand(MBBI->getOperand(i));
// Delete the pseudo instruction TC_RETURN.
MachineInstr *NewMI = std::prev(MBBI);
MBB.erase(MBBI);
MBBI = NewMI;
// For a tail-call in a callee-pops-arguments environment, some or all of
// the stack may actually be in use for the call's arguments, this is
// calculated during LowerCall and consumed here...
ArgumentPopSize = StackAdjust.getImm();
} else {
// ... otherwise the amount to pop is *all* of the argument space,
// conveniently stored in the MachineFunctionInfo by
// LowerFormalArguments. This will, of course, be zero for the C calling
// convention.
ArgumentPopSize = FuncInfo->getArgumentStackToRestore();
}
assert(NumInitialBytes % 16 == 0 && NumResidualBytes % 16 == 0
&& "refusing to adjust stack by misaligned amt");
// We may need to address callee-saved registers differently, so find out the
// bound on the frame indices.
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
int MinCSFI = 0;
int MaxCSFI = -1;
if (CSI.size()) {
MinCSFI = CSI[0].getFrameIdx();
MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
}
// The "residual" stack update comes first from this direction and guarantees
// that SP is NumInitialBytes below its value on function entry, either by a
// direct update or restoring it from the frame pointer.
if (NumInitialBytes + ArgumentPopSize != 0) {
emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16,
NumInitialBytes + ArgumentPopSize);
--MBBI;
}
// MBBI now points to the instruction just past the last callee-saved
// restoration (either RET/B if NumInitialBytes == 0, or the "ADD sp, sp"
// otherwise).
// Now we need to find out where to put the bulk of the stack adjustment
MachineBasicBlock::iterator FirstEpilogue = MBBI;
while (MBBI != MBB.begin()) {
--MBBI;
unsigned FrameOp;
for (FrameOp = 0; FrameOp < MBBI->getNumOperands(); ++FrameOp) {
if (MBBI->getOperand(FrameOp).isFI())
break;
}
// If this instruction doesn't have a frame index we've reached the end of
// the callee-save restoration.
if (FrameOp == MBBI->getNumOperands())
break;
// Likewise if it *is* a local reference, but not to a callee-saved object.
int FrameIdx = MBBI->getOperand(FrameOp).getIndex();
if (FrameIdx < MinCSFI || FrameIdx > MaxCSFI)
break;
FirstEpilogue = MBBI;
}
if (MF.getFrameInfo()->hasVarSizedObjects()) {
int64_t StaticFrameBase;
StaticFrameBase = -(NumInitialBytes + FuncInfo->getFramePointerOffset());
emitRegUpdate(MBB, FirstEpilogue, DL, TII,
AArch64::XSP, AArch64::X29, AArch64::NoRegister,
StaticFrameBase);
} else {
emitSPUpdate(MBB, FirstEpilogue, DL,TII, AArch64::X16, NumResidualBytes);
}
}
int64_t
AArch64FrameLowering::resolveFrameIndexReference(MachineFunction &MF,
int FrameIndex,
unsigned &FrameReg,
int SPAdj,
bool IsCalleeSaveOp) const {
AArch64MachineFunctionInfo *FuncInfo =
MF.getInfo<AArch64MachineFunctionInfo>();
MachineFrameInfo *MFI = MF.getFrameInfo();
int64_t TopOfFrameOffset = MFI->getObjectOffset(FrameIndex);
assert(!(IsCalleeSaveOp && FuncInfo->getInitialStackAdjust() == 0)
&& "callee-saved register in unexpected place");
// If the frame for this function is particularly large, we adjust the stack
// in two phases which means the callee-save related operations see a
// different (intermediate) stack size.
int64_t FrameRegPos;
if (IsCalleeSaveOp) {
FrameReg = AArch64::XSP;
FrameRegPos = -static_cast<int64_t>(FuncInfo->getInitialStackAdjust());
} else if (useFPForAddressing(MF)) {
// Have to use the frame pointer since we have no idea where SP is.
FrameReg = AArch64::X29;
FrameRegPos = FuncInfo->getFramePointerOffset();
} else {
FrameReg = AArch64::XSP;
FrameRegPos = -static_cast<int64_t>(MFI->getStackSize()) + SPAdj;
}
return TopOfFrameOffset - FrameRegPos;
}
void
AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
const AArch64RegisterInfo *RegInfo =
static_cast<const AArch64RegisterInfo *>(MF.getTarget().getRegisterInfo());
MachineFrameInfo *MFI = MF.getFrameInfo();
const AArch64InstrInfo &TII =
*static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
if (hasFP(MF)) {
MF.getRegInfo().setPhysRegUsed(AArch64::X29);
MF.getRegInfo().setPhysRegUsed(AArch64::X30);
}
// If addressing of local variables is going to be more complicated than
// shoving a base register and an offset into the instruction then we may well
// need to scavenge registers. We should either specifically add an
// callee-save register for this purpose or allocate an extra spill slot.
bool BigStack =
MFI->estimateStackSize(MF) >= TII.estimateRSStackLimit(MF)
|| MFI->hasVarSizedObjects() // Access will be from X29: messes things up
|| (MFI->adjustsStack() && !hasReservedCallFrame(MF));
if (!BigStack)
return;
// We certainly need some slack space for the scavenger, preferably an extra
// register.
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
MCPhysReg ExtraReg = AArch64::NoRegister;
for (unsigned i = 0; CSRegs[i]; ++i) {
if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
!MF.getRegInfo().isPhysRegUsed(CSRegs[i])) {
ExtraReg = CSRegs[i];
break;
}
}
if (ExtraReg != 0) {
MF.getRegInfo().setPhysRegUsed(ExtraReg);
} else {
assert(RS && "Expect register scavenger to be available");
// Create a stack slot for scavenging purposes. PrologEpilogInserter
// helpfully places it near either SP or FP for us to avoid
// infinitely-regression during scavenging.
const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
RC->getAlignment(),
false));
}
}
bool AArch64FrameLowering::determinePrologueDeath(MachineBasicBlock &MBB,
unsigned Reg) const {
// If @llvm.returnaddress is called then it will refer to X30 by some means;
// the prologue store does not kill the register.
if (Reg == AArch64::X30) {
if (MBB.getParent()->getFrameInfo()->isReturnAddressTaken()
&& MBB.getParent()->getRegInfo().isLiveIn(Reg))
return false;
}
// In all other cases, physical registers are dead after they've been saved
// but live at the beginning of the prologue block.
MBB.addLiveIn(Reg);
return true;
}
void
AArch64FrameLowering::emitFrameMemOps(bool isPrologue, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI,
const LoadStoreMethod PossClasses[],
unsigned NumClasses) const {
DebugLoc DL = MBB.findDebugLoc(MBBI);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
// A certain amount of implicit contract is present here. The actual stack
// offsets haven't been allocated officially yet, so for strictly correct code
// we rely on the fact that the elements of CSI are allocated in order
// starting at SP, purely as dictated by size and alignment. In practice since
// this function handles the only accesses to those slots it's not quite so
// important.
//
// We have also ordered the Callee-saved register list in AArch64CallingConv
// so that the above scheme puts registers in order: in particular we want
// &X30 to be &X29+8 for an ABI-correct frame record (PCS 5.2.2)
for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
unsigned Reg = CSI[i].getReg();
// First we need to find out which register class the register belongs to so
// that we can use the correct load/store instrucitons.
unsigned ClassIdx;
for (ClassIdx = 0; ClassIdx < NumClasses; ++ClassIdx) {
if (PossClasses[ClassIdx].RegClass->contains(Reg))
break;
}
assert(ClassIdx != NumClasses
&& "Asked to store register in unexpected class");
const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
// Now we need to decide whether it's possible to emit a paired instruction:
// for this we want the next register to be in the same class.
MachineInstrBuilder NewMI;
bool Pair = false;
if (i + 1 < CSI.size() && TheClass.contains(CSI[i+1].getReg())) {
Pair = true;
unsigned StLow = 0, StHigh = 0;
if (isPrologue) {
// Most of these registers will be live-in to the MBB and killed by our
// store, though there are exceptions (see determinePrologueDeath).
StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg()));
StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
} else {
StLow = RegState::Define;
StHigh = RegState::Define;
}
NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].PairOpcode))
.addReg(CSI[i+1].getReg(), StLow)
.addReg(CSI[i].getReg(), StHigh);
// If it's a paired op, we've consumed two registers
++i;
} else {
unsigned State;
if (isPrologue) {
State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
} else {
State = RegState::Define;
}
NewMI = BuildMI(MBB, MBBI, DL,
TII.get(PossClasses[ClassIdx].SingleOpcode))
.addReg(CSI[i].getReg(), State);
}
// Note that the FrameIdx refers to the second register in a pair: it will
// be allocated the smaller numeric address and so is the one an LDP/STP
// address must use.
int FrameIdx = CSI[i].getFrameIdx();
MachineMemOperand::MemOperandFlags Flags;
Flags = isPrologue ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
MachineMemOperand *MMO =
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
Flags,
Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
MFI.getObjectAlignment(FrameIdx));
NewMI.addFrameIndex(FrameIdx)
.addImm(0) // address-register offset
.addMemOperand(MMO);
if (isPrologue)
NewMI.setMIFlags(MachineInstr::FrameSetup);
// For aesthetic reasons, during an epilogue we want to emit complementary
// operations to the prologue, but in the opposite order. So we still
// iterate through the CalleeSavedInfo list in order, but we put the
// instructions successively earlier in the MBB.
if (!isPrologue)
--MBBI;
}
}
bool
AArch64FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
if (CSI.empty())
return false;
static const LoadStoreMethod PossibleClasses[] = {
{&AArch64::GPR64RegClass, AArch64::LSPair64_STR, AArch64::LS64_STR},
{&AArch64::FPR64RegClass, AArch64::LSFPPair64_STR, AArch64::LSFP64_STR},
};
const unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
emitFrameMemOps(/* isPrologue = */ true, MBB, MBBI, CSI, TRI,
PossibleClasses, NumClasses);
return true;
}
bool
AArch64FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
if (CSI.empty())
return false;
static const LoadStoreMethod PossibleClasses[] = {
{&AArch64::GPR64RegClass, AArch64::LSPair64_LDR, AArch64::LS64_LDR},
{&AArch64::FPR64RegClass, AArch64::LSFPPair64_LDR, AArch64::LSFP64_LDR},
};
const unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
emitFrameMemOps(/* isPrologue = */ false, MBB, MBBI, CSI, TRI,
PossibleClasses, NumClasses);
return true;
}
bool
AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
// This is a decision of ABI compliance. The AArch64 PCS gives various options
// for conformance, and even at the most stringent level more or less permits
// elimination for leaf functions because there's no loss of functionality
// (for debugging etc)..
if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->hasCalls())
return true;
// The following are hard-limits: incorrect code will be generated if we try
// to omit the frame.
return (RI->needsStackRealignment(MF) ||
MFI->hasVarSizedObjects() ||
MFI->isFrameAddressTaken());
}
bool
AArch64FrameLowering::useFPForAddressing(const MachineFunction &MF) const {
return MF.getFrameInfo()->hasVarSizedObjects();
}
bool
AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
// Of the various reasons for having a frame pointer, it's actually only
// variable-sized objects that prevent reservation of a call frame.
return !(hasFP(MF) && MFI->hasVarSizedObjects());
}
void
AArch64FrameLowering::eliminateCallFramePseudoInstr(
MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
const AArch64InstrInfo &TII =
*static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
DebugLoc dl = MI->getDebugLoc();
int Opcode = MI->getOpcode();
bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
uint64_t CalleePopAmount = IsDestroy ? MI->getOperand(1).getImm() : 0;
if (!hasReservedCallFrame(MF)) {
unsigned Align = getStackAlignment();
int64_t Amount = MI->getOperand(0).getImm();
Amount = RoundUpToAlignment(Amount, Align);
if (!IsDestroy) Amount = -Amount;
// N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
// doesn't have to pop anything), then the first operand will be zero too so
// this adjustment is a no-op.
if (CalleePopAmount == 0) {
// FIXME: in-function stack adjustment for calls is limited to 12-bits
// because there's no guaranteed temporary register available. Mostly call
// frames will be allocated at the start of a function so this is OK, but
// it is a limitation that needs dealing with.
assert(Amount > -0xfff && Amount < 0xfff && "call frame too large");
emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
}
} else if (CalleePopAmount != 0) {
// If the calling convention demands that the callee pops arguments from the
// stack, we want to add it back if we have a reserved call frame.
assert(CalleePopAmount < 0xfff && "call frame too large");
emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, -CalleePopAmount);
}
MBB.erase(MI);
}

108
lib/Target/AArch64/AArch64FrameLowering.h
View File

@ -1,108 +0,0 @@
//==- AArch64FrameLowering.h - Define frame lowering for AArch64 -*- C++ -*--=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class implements the AArch64-specific parts of the TargetFrameLowering
// class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64_FRAMEINFO_H
#define LLVM_AARCH64_FRAMEINFO_H
#include "AArch64Subtarget.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class AArch64Subtarget;
class AArch64FrameLowering : public TargetFrameLowering {
private:
// In order to unify the spilling and restoring of callee-saved registers into
// emitFrameMemOps, we need to be able to specify which instructions to use
// for the relevant memory operations on each register class. An array of the
// following struct is populated and passed in to achieve this.
struct LoadStoreMethod {
const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
// The preferred instruction.
unsigned PairOpcode; // E.g. LSPair64_STR
// Sometimes only a single register can be handled at once.
unsigned SingleOpcode; // E.g. LS64_STR
};
protected:
const AArch64Subtarget &STI;
public:
explicit AArch64FrameLowering(const AArch64Subtarget &sti)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0, 16),
STI(sti) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
/// Decides how much stack adjustment to perform in each phase of the prologue
/// and epilogue.
void splitSPAdjustments(uint64_t Total, uint64_t &Initial,
uint64_t &Residual) const;
int64_t resolveFrameIndexReference(MachineFunction &MF, int FrameIndex,
unsigned &FrameReg, int SPAdj,
bool IsCalleeSaveOp) const;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const override;
void
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
/// If the register is X30 (i.e. LR) and the return address is used in the
/// function then the callee-save store doesn't actually kill the register,
/// otherwise it does.
bool determinePrologueDeath(MachineBasicBlock &MBB, unsigned Reg) const;
/// This function emits the loads or stores required during prologue and
/// epilogue as efficiently as possible.
///
/// The operations involved in setting up and tearing down the frame are
/// similar enough to warrant a shared function, particularly as discrepancies
/// between the two would be disastrous.
void emitFrameMemOps(bool isStore, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI,
const LoadStoreMethod PossibleClasses[],
unsigned NumClasses) const;
bool hasFP(const MachineFunction &MF) const override;
bool useFPForAddressing(const MachineFunction &MF) const;
/// On AA
bool hasReservedCallFrame(const MachineFunction &MF) const override;
};
} // End llvm namespace
#endif

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//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the interfaces that AArch64 uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H
#define LLVM_TARGET_AARCH64_ISELLOWERING_H
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
namespace AArch64ISD {
enum NodeType {
// Start the numbering from where ISD NodeType finishes.
FIRST_NUMBER = ISD::BUILTIN_OP_END,
// This is a conditional branch which also notes the flag needed
// (eq/sgt/...). A64 puts this information on the branches rather than
// compares as LLVM does.
BR_CC,
// A node to be selected to an actual call operation: either BL or BLR in
// the absence of tail calls.
Call,
// Indicates a floating-point immediate which fits into the format required
// by the FMOV instructions. First (and only) operand is the 8-bit encoded
// value of that immediate.
FPMOV,
// Corresponds directly to an EXTR instruction. Operands are an LHS an RHS
// and an LSB.
EXTR,
// Wraps a load from the GOT, which should always be performed with a 64-bit
// load instruction. This prevents the DAG combiner folding a truncate to
// form a smaller memory access.
GOTLoad,
// Performs a bitfield insert. Arguments are: the value being inserted into;
// the value being inserted; least significant bit changed; width of the
// field.
BFI,
// Simply a convenient node inserted during ISelLowering to represent
// procedure return. Will almost certainly be selected to "RET".
Ret,
/// Extracts a field of contiguous bits from the source and sign extends
/// them into a single register. Arguments are: source; immr; imms. Note
/// these are pre-encoded since DAG matching can't cope with combining LSB
/// and Width into these values itself.
SBFX,
/// This is an A64-ification of the standard LLVM SELECT_CC operation. The
/// main difference is that it only has the values and an A64 condition,
/// which will be produced by a setcc instruction.
SELECT_CC,
/// This serves most of the functions of the LLVM SETCC instruction, for two
/// purposes. First, it prevents optimisations from fiddling with the
/// compare after we've moved the CondCode information onto the SELECT_CC or
/// BR_CC instructions. Second, it gives a legal instruction for the actual
/// comparison.
///
/// It keeps a record of the condition flags asked for because certain
/// instructions are only valid for a subset of condition codes.
SETCC,
// Designates a node which is a tail call: both a call and a return
// instruction as far as selction is concerned. It should be selected to an
// unconditional branch. Has the usual plethora of call operands, but: 1st
// is callee, 2nd is stack adjustment required immediately before branch.
TC_RETURN,
// Designates a call used to support the TLS descriptor ABI. The call itself
// will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall
// var") must be attached somehow during code generation. It takes two
// operands: the callee and the symbol to be relocated against.
TLSDESCCALL,
// Leaf node which will be lowered to an appropriate MRS to obtain the
// thread pointer: TPIDR_EL0.
THREAD_POINTER,
/// Extracts a field of contiguous bits from the source and zero extends
/// them into a single register. Arguments are: source; immr; imms. Note
/// these are pre-encoded since DAG matching can't cope with combining LSB
/// and Width into these values itself.
UBFX,
// Wraps an address which the ISelLowering phase has decided should be
// created using the large memory model style: i.e. a sequence of four
// movz/movk instructions.
WrapperLarge,
// Wraps an address which the ISelLowering phase has decided should be
// created using the small memory model style: i.e. adrp/add or
// adrp/mem-op. This exists to prevent bare TargetAddresses which may never
// get selected.
WrapperSmall,
// Vector move immediate
NEON_MOVIMM,
// Vector Move Inverted Immediate
NEON_MVNIMM,
// Vector FP move immediate
NEON_FMOVIMM,
// Vector permute
NEON_UZP1,
NEON_UZP2,
NEON_ZIP1,
NEON_ZIP2,
NEON_TRN1,
NEON_TRN2,
// Vector Element reverse
NEON_REV64,
NEON_REV32,
NEON_REV16,
// Vector compare
NEON_CMP,
// Vector compare zero
NEON_CMPZ,
// Vector compare bitwise test
NEON_TST,
// Vector saturating shift
NEON_QSHLs,
NEON_QSHLu,
// Vector dup
NEON_VDUP,
// Vector dup by lane
NEON_VDUPLANE,
// Vector extract
NEON_VEXTRACT,
// NEON duplicate lane loads
NEON_LD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
NEON_LD3DUP,
NEON_LD4DUP,
// NEON loads with post-increment base updates:
NEON_LD1_UPD,
NEON_LD2_UPD,
NEON_LD3_UPD,
NEON_LD4_UPD,
NEON_LD1x2_UPD,
NEON_LD1x3_UPD,
NEON_LD1x4_UPD,
// NEON stores with post-increment base updates:
NEON_ST1_UPD,
NEON_ST2_UPD,
NEON_ST3_UPD,
NEON_ST4_UPD,
NEON_ST1x2_UPD,
NEON_ST1x3_UPD,
NEON_ST1x4_UPD,
// NEON duplicate lane loads with post-increment base updates:
NEON_LD2DUP_UPD,
NEON_LD3DUP_UPD,
NEON_LD4DUP_UPD,
// NEON lane loads with post-increment base updates:
NEON_LD2LN_UPD,
NEON_LD3LN_UPD,
NEON_LD4LN_UPD,
// NEON lane store with post-increment base updates:
NEON_ST2LN_UPD,
NEON_ST3LN_UPD,
NEON_ST4LN_UPD
};
}
class AArch64Subtarget;
class AArch64TargetMachine;
class AArch64TargetLowering : public TargetLowering {
public:
explicit AArch64TargetLowering(AArch64TargetMachine &TM);
const char *getTargetNodeName(unsigned Opcode) const override;
CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
SDValue LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const override;
unsigned getByValTypeAlignment(Type *Ty) const override;
SDValue LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
bool isConcatVector(SDValue Op, SelectionDAG &DAG, SDValue V0, SDValue V1,
const int *Mask, SDValue &Res) const;
bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &V0,
SDValue &V1, int *Mask) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
const AArch64Subtarget *ST) const;
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
SDValue &Chain) const;
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Targets which want to do tail call
/// optimization should implement this function.
bool IsEligibleForTailCallOptimization(SDValue Callee,
CallingConv::ID CalleeCC,
bool IsVarArg,
bool IsCalleeStructRet,
bool IsCallerStructRet,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
/// Finds the incoming stack arguments which overlap the given fixed stack
/// object and incorporates their load into the current chain. This prevents
/// an upcoming store from clobbering the stack argument before it's used.
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
MachineFrameInfo *MFI, int ClobberedFI) const;
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
bool IsTailCallConvention(CallingConv::ID CallCC) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
bool isLegalICmpImmediate(int64_t Val) const override;
/// \brief Return true if the addressing mode represented by AM is legal for
/// this target, for a load/store of the specified type.
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
/// \brief Return the cost of the scaling factor used in the addressing
/// mode represented by AM for this target, for a load/store
/// of the specified type.
/// If the AM is supported, the return value must be >= 0.
/// If the AM is not supported, it returns a negative value.
int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
bool isTruncateFree(EVT VT1, EVT VT2) const override;
bool isZExtFree(Type *Ty1, Type *Ty2) const override;
bool isZExtFree(EVT VT1, EVT VT2) const override;
bool isZExtFree(SDValue Val, EVT VT2) const override;
SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
MachineBasicBlock *
emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
unsigned Size, unsigned Opcode) const;
MachineBasicBlock *
emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size, unsigned CmpOp,
A64CC::CondCodes Cond) const;
MachineBasicBlock *
emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size) const;
MachineBasicBlock *
EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const;
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
RTLIB::Libcall Call) const;
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue PerformDAGCombine(SDNode *N,DAGCombinerInfo &DCI) const override;
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
/// expanded to FMAs when this method returns true, otherwise fmuladd is
/// expanded to fmul + fadd.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
/// unaligned memory accesses of the specified type. Returns whether it
/// is "fast" by reference in the second argument.
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const override;
ConstraintType
getConstraintType(const std::string &Constraint) const override;
ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo &Info,
const char *Constraint) const override;
void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const override;
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
unsigned Intrinsic) const override;
/// getMaximalGlobalOffset - Returns the maximal possible offset which can
/// be used for loads / stores from the global.
unsigned getMaximalGlobalOffset() const override;
protected:
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const override;
private:
const InstrItineraryData *Itins;
const AArch64Subtarget *getSubtarget() const {
return &getTargetMachine().getSubtarget<AArch64Subtarget>();
}
};
enum NeonModImmType {
Neon_Mov_Imm,
Neon_Mvn_Imm
};
extern SDValue ScanBUILD_VECTOR(SDValue Op, bool &isOnlyLowElement,
bool &usesOnlyOneValue, bool &hasDominantValue,
bool &isConstant, bool &isUNDEF);
} // namespace llvm
#endif // LLVM_TARGET_AARCH64_ISELLOWERING_H

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//===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include <algorithm>
using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "AArch64GenInstrInfo.inc"
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
: AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
Subtarget(STI) {}
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
unsigned Opc = 0;
unsigned ZeroReg = 0;
if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
// E.g. ADD xDst, xsp, #0 (, lsl #0)
BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
.addReg(SrcReg)
.addImm(0);
return;
} else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
// E.g. ADD wDST, wsp, #0 (, lsl #0)
BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
.addReg(SrcReg)
.addImm(0);
return;
} else if (DestReg == AArch64::NZCV) {
assert(AArch64::GPR64RegClass.contains(SrcReg));
// E.g. MSR NZCV, xDST
BuildMI(MBB, I, DL, get(AArch64::MSRix))
.addImm(A64SysReg::NZCV)
.addReg(SrcReg);
} else if (SrcReg == AArch64::NZCV) {
assert(AArch64::GPR64RegClass.contains(DestReg));
// E.g. MRS xDST, NZCV
BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
.addImm(A64SysReg::NZCV);
} else if (AArch64::GPR64RegClass.contains(DestReg)) {
if(AArch64::GPR64RegClass.contains(SrcReg)){
Opc = AArch64::ORRxxx_lsl;
ZeroReg = AArch64::XZR;
} else{
assert(AArch64::FPR64RegClass.contains(SrcReg));
BuildMI(MBB, I, DL, get(AArch64::FMOVxd), DestReg)
.addReg(SrcReg);
return;
}
} else if (AArch64::GPR32RegClass.contains(DestReg)) {
if(AArch64::GPR32RegClass.contains(SrcReg)){
Opc = AArch64::ORRwww_lsl;
ZeroReg = AArch64::WZR;
} else{
assert(AArch64::FPR32RegClass.contains(SrcReg));
BuildMI(MBB, I, DL, get(AArch64::FMOVws), DestReg)
.addReg(SrcReg);
return;
}
} else if (AArch64::FPR32RegClass.contains(DestReg)) {
if(AArch64::FPR32RegClass.contains(SrcReg)){
BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
.addReg(SrcReg);
return;
}
else {
assert(AArch64::GPR32RegClass.contains(SrcReg));
BuildMI(MBB, I, DL, get(AArch64::FMOVsw), DestReg)
.addReg(SrcReg);
return;
}
} else if (AArch64::FPR64RegClass.contains(DestReg)) {
if(AArch64::FPR64RegClass.contains(SrcReg)){
BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
.addReg(SrcReg);
return;
}
else {
assert(AArch64::GPR64RegClass.contains(SrcReg));
BuildMI(MBB, I, DL, get(AArch64::FMOVdx), DestReg)
.addReg(SrcReg);
return;
}
} else if (AArch64::FPR128RegClass.contains(DestReg)) {
assert(AArch64::FPR128RegClass.contains(SrcReg));
// If NEON is enable, we use ORR to implement this copy.
// If NEON isn't available, emit STR and LDR to handle this.
if(getSubTarget().hasNEON()) {
BuildMI(MBB, I, DL, get(AArch64::ORRvvv_16B), DestReg)
.addReg(SrcReg)
.addReg(SrcReg);
return;
} else {
BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
.addReg(SrcReg)
.addReg(AArch64::XSP)
.addImm(0x1ff & -16);
BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
.addReg(AArch64::XSP, RegState::Define)
.addReg(AArch64::XSP)
.addImm(16);
return;
}
} else if (AArch64::FPR8RegClass.contains(DestReg, SrcReg)) {
// The copy of two FPR8 registers is implemented by the copy of two FPR32
const TargetRegisterInfo *TRI = &getRegisterInfo();
unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_8,
&AArch64::FPR32RegClass);
unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_8,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
.addReg(Src);
return;
} else if (AArch64::FPR16RegClass.contains(DestReg, SrcReg)) {
// The copy of two FPR16 registers is implemented by the copy of two FPR32
const TargetRegisterInfo *TRI = &getRegisterInfo();
unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
&AArch64::FPR32RegClass);
unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
&AArch64::FPR32RegClass);
BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
.addReg(Src);
return;
} else {
CopyPhysRegTuple(MBB, I, DL, DestReg, SrcReg);
return;
}
// E.g. ORR xDst, xzr, xSrc, lsl #0
BuildMI(MBB, I, DL, get(Opc), DestReg)
.addReg(ZeroReg)
.addReg(SrcReg)
.addImm(0);
}
void AArch64InstrInfo::CopyPhysRegTuple(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
DebugLoc DL, unsigned DestReg,
unsigned SrcReg) const {
unsigned SubRegs;
bool IsQRegs;
if (AArch64::DPairRegClass.contains(DestReg, SrcReg)) {
SubRegs = 2;
IsQRegs = false;
} else if (AArch64::DTripleRegClass.contains(DestReg, SrcReg)) {
SubRegs = 3;
IsQRegs = false;
} else if (AArch64::DQuadRegClass.contains(DestReg, SrcReg)) {
SubRegs = 4;
IsQRegs = false;
} else if (AArch64::QPairRegClass.contains(DestReg, SrcReg)) {
SubRegs = 2;
IsQRegs = true;
} else if (AArch64::QTripleRegClass.contains(DestReg, SrcReg)) {
SubRegs = 3;
IsQRegs = true;
} else if (AArch64::QQuadRegClass.contains(DestReg, SrcReg)) {
SubRegs = 4;
IsQRegs = true;
} else
llvm_unreachable("Unknown register class");
unsigned BeginIdx = IsQRegs ? AArch64::qsub_0 : AArch64::dsub_0;
int Spacing = 1;
const TargetRegisterInfo *TRI = &getRegisterInfo();
// Copy register tuples backward when the first Dest reg overlaps
// with SrcReg.
if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
BeginIdx = BeginIdx + (SubRegs - 1);
Spacing = -1;
}
unsigned Opc = IsQRegs ? AArch64::ORRvvv_16B : AArch64::ORRvvv_8B;
for (unsigned i = 0; i != SubRegs; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
assert(Dst && Src && "Bad sub-register");
BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
.addReg(Src)
.addReg(Src);
}
return;
}
/// Does the Opcode represent a conditional branch that we can remove and re-add
/// at the end of a basic block?
static bool isCondBranch(unsigned Opc) {
return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
Opc == AArch64::CBNZw || Opc == AArch64::CBNZx ||
Opc == AArch64::TBZwii || Opc == AArch64::TBZxii ||
Opc == AArch64::TBNZwii || Opc == AArch64::TBNZxii;
}
/// Takes apart a given conditional branch MachineInstr (see isCondBranch),
/// setting TBB to the destination basic block and populating the Cond vector
/// with data necessary to recreate the conditional branch at a later
/// date. First element will be the opcode, and subsequent ones define the
/// conditions being branched on in an instruction-specific manner.
static void classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB,
SmallVectorImpl<MachineOperand> &Cond) {
switch(I->getOpcode()) {
case AArch64::Bcc:
case AArch64::CBZw:
case AArch64::CBZx:
case AArch64::CBNZw:
case AArch64::CBNZx:
// These instructions just have one predicate operand in position 0 (either
// a condition code or a register being compared).
Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
Cond.push_back(I->getOperand(0));
TBB = I->getOperand(1).getMBB();
return;
case AArch64::TBZwii:
case AArch64::TBZxii:
case AArch64::TBNZwii:
case AArch64::TBNZxii:
// These have two predicate operands: a register and a bit position.
Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
Cond.push_back(I->getOperand(0));
Cond.push_back(I->getOperand(1));
TBB = I->getOperand(2).getMBB();
return;
default:
llvm_unreachable("Unknown conditional branch to classify");
}
}
bool
AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin())
return false;
--I;
while (I->isDebugValue()) {
if (I == MBB.begin())
return false;
--I;
}
if (!isUnpredicatedTerminator(I))
return false;
// Get the last instruction in the block.
MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastOpc == AArch64::Bimm) {
TBB = LastInst->getOperand(0).getMBB();
return false;
}
if (isCondBranch(LastOpc)) {
classifyCondBranch(LastInst, TBB, Cond);
return false;
}
return true; // Can't handle indirect branch.
}
// Get the instruction before it if it is a terminator.
MachineInstr *SecondLastInst = I;
unsigned SecondLastOpc = SecondLastInst->getOpcode();
// If AllowModify is true and the block ends with two or more unconditional
// branches, delete all but the first unconditional branch.
if (AllowModify && LastOpc == AArch64::Bimm) {
while (SecondLastOpc == AArch64::Bimm) {
LastInst->eraseFromParent();
LastInst = SecondLastInst;
LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
// Return now the only terminator is an unconditional branch.
TBB = LastInst->getOperand(0).getMBB();
return false;
} else {
SecondLastInst = I;
SecondLastOpc = SecondLastInst->getOpcode();
}
}
}
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
return true;
// If the block ends with a B and a Bcc, handle it.
if (LastOpc == AArch64::Bimm) {
if (SecondLastOpc == AArch64::Bcc) {
TBB = SecondLastInst->getOperand(1).getMBB();
Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
Cond.push_back(SecondLastInst->getOperand(0));
FBB = LastInst->getOperand(0).getMBB();
return false;
} else if (isCondBranch(SecondLastOpc)) {
classifyCondBranch(SecondLastInst, TBB, Cond);
FBB = LastInst->getOperand(0).getMBB();
return false;
}
}
// If the block ends with two unconditional branches, handle it. The second
// one is not executed, so remove it.
if (SecondLastOpc == AArch64::Bimm && LastOpc == AArch64::Bimm) {
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
if (AllowModify)
I->eraseFromParent();
return false;
}
// Otherwise, can't handle this.
return true;
}
bool AArch64InstrInfo::ReverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const {
switch (Cond[0].getImm()) {
case AArch64::Bcc: {
A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
CC = A64InvertCondCode(CC);
Cond[1].setImm(CC);
return false;
}
case AArch64::CBZw:
Cond[0].setImm(AArch64::CBNZw);
return false;
case AArch64::CBZx:
Cond[0].setImm(AArch64::CBNZx);
return false;
case AArch64::CBNZw:
Cond[0].setImm(AArch64::CBZw);
return false;
case AArch64::CBNZx:
Cond[0].setImm(AArch64::CBZx);
return false;
case AArch64::TBZwii:
Cond[0].setImm(AArch64::TBNZwii);
return false;
case AArch64::TBZxii:
Cond[0].setImm(AArch64::TBNZxii);
return false;
case AArch64::TBNZwii:
Cond[0].setImm(AArch64::TBZwii);
return false;
case AArch64::TBNZxii:
Cond[0].setImm(AArch64::TBZxii);
return false;
default:
llvm_unreachable("Unknown branch type");
}
}
unsigned
AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const {
if (!FBB && Cond.empty()) {
BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
return 1;
} else if (!FBB) {
MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
for (int i = 1, e = Cond.size(); i != e; ++i)
MIB.addOperand(Cond[i]);
MIB.addMBB(TBB);
return 1;
}
MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
for (int i = 1, e = Cond.size(); i != e; ++i)
MIB.addOperand(Cond[i]);
MIB.addMBB(TBB);
BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
return 2;
}
unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin()) return 0;
--I;
while (I->isDebugValue()) {
if (I == MBB.begin())
return 0;
--I;
}
if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode()))
return 0;
// Remove the branch.
I->eraseFromParent();
I = MBB.end();
if (I == MBB.begin()) return 1;
--I;
if (!isCondBranch(I->getOpcode()))
return 1;
// Remove the branch.
I->eraseFromParent();
return 2;
}
bool
AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;
MachineBasicBlock &MBB = *MI.getParent();
unsigned Opcode = MI.getOpcode();
switch (Opcode) {
case AArch64::TLSDESC_BLRx: {
MachineInstr *NewMI =
BuildMI(MBB, MBBI, MI.getDebugLoc(), get(AArch64::TLSDESCCALL))
.addOperand(MI.getOperand(1));
MI.setDesc(get(AArch64::BLRx));
llvm::finalizeBundle(MBB, NewMI, *++MBBI);
return true;
}
default:
return false;
}
return false;
}
void
AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill,
int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
DebugLoc DL = MBB.findDebugLoc(MBBI);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FrameIdx);
MachineMemOperand *MMO
= MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
MachineMemOperand::MOStore,
MFI.getObjectSize(FrameIdx),
Align);
unsigned StoreOp = 0;
if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
switch(RC->getSize()) {
case 4: StoreOp = AArch64::LS32_STR; break;
case 8: StoreOp = AArch64::LS64_STR; break;
default:
llvm_unreachable("Unknown size for regclass");
}
} else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
StoreOp = AArch64::LSFP8_STR;
} else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
StoreOp = AArch64::LSFP16_STR;
} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
RC->hasType(MVT::f128)) {
switch (RC->getSize()) {
case 4: StoreOp = AArch64::LSFP32_STR; break;
case 8: StoreOp = AArch64::LSFP64_STR; break;
case 16: StoreOp = AArch64::LSFP128_STR; break;
default:
llvm_unreachable("Unknown size for regclass");
}
} else { // For a super register class has more than one sub registers
if (AArch64::DPairRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x2_8B;
else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x3_8B;
else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x4_8B;
else if (AArch64::QPairRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x2_16B;
else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x3_16B;
else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
StoreOp = AArch64::ST1x4_16B;
else
llvm_unreachable("Unknown reg class");
MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
// Vector store has different operands from other store instructions.
NewMI.addFrameIndex(FrameIdx)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO);
return;
}
MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
NewMI.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FrameIdx)
.addImm(0)
.addMemOperand(MMO);
}
void
AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
DebugLoc DL = MBB.findDebugLoc(MBBI);
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FrameIdx);
MachineMemOperand *MMO
= MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
MachineMemOperand::MOLoad,
MFI.getObjectSize(FrameIdx),
Align);
unsigned LoadOp = 0;
if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
switch(RC->getSize()) {
case 4: LoadOp = AArch64::LS32_LDR; break;
case 8: LoadOp = AArch64::LS64_LDR; break;
default:
llvm_unreachable("Unknown size for regclass");
}
} else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
LoadOp = AArch64::LSFP8_LDR;
} else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
LoadOp = AArch64::LSFP16_LDR;
} else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
RC->hasType(MVT::f128)) {
switch (RC->getSize()) {
case 4: LoadOp = AArch64::LSFP32_LDR; break;
case 8: LoadOp = AArch64::LSFP64_LDR; break;
case 16: LoadOp = AArch64::LSFP128_LDR; break;
default:
llvm_unreachable("Unknown size for regclass");
}
} else { // For a super register class has more than one sub registers
if (AArch64::DPairRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x2_8B;
else if (AArch64::DTripleRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x3_8B;
else if (AArch64::DQuadRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x4_8B;
else if (AArch64::QPairRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x2_16B;
else if (AArch64::QTripleRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x3_16B;
else if (AArch64::QQuadRegClass.hasSubClassEq(RC))
LoadOp = AArch64::LD1x4_16B;
else
llvm_unreachable("Unknown reg class");
MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
// Vector load has different operands from other load instructions.
NewMI.addFrameIndex(FrameIdx)
.addMemOperand(MMO);
return;
}
MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
NewMI.addFrameIndex(FrameIdx)
.addImm(0)
.addMemOperand(MMO);
}
unsigned AArch64InstrInfo::estimateRSStackLimit(MachineFunction &MF) const {
unsigned Limit = (1 << 16) - 1;
for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
I != E; ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
if (!I->getOperand(i).isFI()) continue;
// When using ADDxxi_lsl0_s to get the address of a stack object, 0xfff
// is the largest offset guaranteed to fit in the immediate offset.
if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
Limit = std::min(Limit, 0xfffu);
break;
}
int AccessScale, MinOffset, MaxOffset;
getAddressConstraints(*I, AccessScale, MinOffset, MaxOffset);
Limit = std::min(Limit, static_cast<unsigned>(MaxOffset));
break; // At most one FI per instruction
}
}
}
return Limit;
}
void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
int &AccessScale, int &MinOffset,
int &MaxOffset) const {
switch (MI.getOpcode()) {
default:
llvm_unreachable("Unknown load/store kind");
case TargetOpcode::DBG_VALUE:
AccessScale = 1;
MinOffset = INT_MIN;
MaxOffset = INT_MAX;
return;
case AArch64::LS8_LDR: case AArch64::LS8_STR:
case AArch64::LSFP8_LDR: case AArch64::LSFP8_STR:
case AArch64::LDRSBw:
case AArch64::LDRSBx:
AccessScale = 1;
MinOffset = 0;
MaxOffset = 0xfff;
return;
case AArch64::LS16_LDR: case AArch64::LS16_STR:
case AArch64::LSFP16_LDR: case AArch64::LSFP16_STR:
case AArch64::LDRSHw:
case AArch64::LDRSHx:
AccessScale = 2;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LS32_LDR: case AArch64::LS32_STR:
case AArch64::LSFP32_LDR: case AArch64::LSFP32_STR:
case AArch64::LDRSWx:
case AArch64::LDPSWx:
AccessScale = 4;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LS64_LDR: case AArch64::LS64_STR:
case AArch64::LSFP64_LDR: case AArch64::LSFP64_STR:
case AArch64::PRFM:
AccessScale = 8;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LSFP128_LDR: case AArch64::LSFP128_STR:
AccessScale = 16;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LSPair32_LDR: case AArch64::LSPair32_STR:
case AArch64::LSFPPair32_LDR: case AArch64::LSFPPair32_STR:
AccessScale = 4;
MinOffset = -0x40 * AccessScale;
MaxOffset = 0x3f * AccessScale;
return;
case AArch64::LSPair64_LDR: case AArch64::LSPair64_STR:
case AArch64::LSFPPair64_LDR: case AArch64::LSFPPair64_STR:
AccessScale = 8;
MinOffset = -0x40 * AccessScale;
MaxOffset = 0x3f * AccessScale;
return;
case AArch64::LSFPPair128_LDR: case AArch64::LSFPPair128_STR:
AccessScale = 16;
MinOffset = -0x40 * AccessScale;
MaxOffset = 0x3f * AccessScale;
return;
case AArch64::LD1x2_8B: case AArch64::ST1x2_8B:
AccessScale = 16;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LD1x3_8B: case AArch64::ST1x3_8B:
AccessScale = 24;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LD1x4_8B: case AArch64::ST1x4_8B:
case AArch64::LD1x2_16B: case AArch64::ST1x2_16B:
AccessScale = 32;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LD1x3_16B: case AArch64::ST1x3_16B:
AccessScale = 48;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
case AArch64::LD1x4_16B: case AArch64::ST1x4_16B:
AccessScale = 64;
MinOffset = 0;
MaxOffset = 0xfff * AccessScale;
return;
}
}
unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MCInstrDesc &MCID = MI.getDesc();
const MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction &MF = *MBB.getParent();
const MCAsmInfo &MAI = *MF.getTarget().getMCAsmInfo();
if (MCID.getSize())
return MCID.getSize();
if (MI.getOpcode() == AArch64::INLINEASM)
return getInlineAsmLength(MI.getOperand(0).getSymbolName(), MAI);
switch (MI.getOpcode()) {
case TargetOpcode::BUNDLE:
return getInstBundleLength(MI);
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::CFI_INSTRUCTION:
case TargetOpcode::EH_LABEL:
case TargetOpcode::GC_LABEL:
case TargetOpcode::DBG_VALUE:
case AArch64::TLSDESCCALL:
return 0;
default:
llvm_unreachable("Unknown instruction class");
}
}
unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const {
unsigned Size = 0;
MachineBasicBlock::const_instr_iterator I = MI;
MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
while (++I != E && I->isInsideBundle()) {
assert(!I->isBundle() && "No nested bundle!");
Size += getInstSizeInBytes(*I);
}
return Size;
}
bool llvm::rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
unsigned FrameReg, int &Offset,
const AArch64InstrInfo &TII) {
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
MFI.getObjectOffset(FrameRegIdx);
llvm_unreachable("Unimplemented rewriteFrameIndex");
}
void llvm::emitRegUpdate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
DebugLoc dl, const TargetInstrInfo &TII,
unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
int64_t NumBytes, MachineInstr::MIFlag MIFlags) {
if (NumBytes == 0 && DstReg == SrcReg)
return;
else if (abs64(NumBytes) & ~0xffffff) {
// Generically, we have to materialize the offset into a temporary register
// and subtract it. There are a couple of ways this could be done, for now
// we'll use a movz/movk or movn/movk sequence.
uint64_t Bits = static_cast<uint64_t>(abs64(NumBytes));
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
.addImm(0xffff & Bits).addImm(0)
.setMIFlags(MIFlags);
Bits >>= 16;
if (Bits & 0xffff) {
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
.addReg(ScratchReg)
.addImm(0xffff & Bits).addImm(1)
.setMIFlags(MIFlags);
}
Bits >>= 16;
if (Bits & 0xffff) {
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
.addReg(ScratchReg)
.addImm(0xffff & Bits).addImm(2)
.setMIFlags(MIFlags);
}
Bits >>= 16;
if (Bits & 0xffff) {
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
.addReg(ScratchReg)
.addImm(0xffff & Bits).addImm(3)
.setMIFlags(MIFlags);
}
// ADD DST, SRC, xTMP (, lsl #0)
unsigned AddOp = NumBytes > 0 ? AArch64::ADDxxx_uxtx : AArch64::SUBxxx_uxtx;
BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg)
.addReg(SrcReg, RegState::Kill)
.addReg(ScratchReg, RegState::Kill)
.addImm(0)
.setMIFlag(MIFlags);
return;
}
// Now we know that the adjustment can be done in at most two add/sub
// (immediate) instructions, which is always more efficient than a
// literal-pool load, or even a hypothetical movz/movk/add sequence
// Decide whether we're doing addition or subtraction
unsigned LowOp, HighOp;
if (NumBytes >= 0) {
LowOp = AArch64::ADDxxi_lsl0_s;
HighOp = AArch64::ADDxxi_lsl12_s;
} else {
LowOp = AArch64::SUBxxi_lsl0_s;
HighOp = AArch64::SUBxxi_lsl12_s;
NumBytes = abs64(NumBytes);
}
// If we're here, at the very least a move needs to be produced, which just
// happens to be materializable by an ADD.
if ((NumBytes & 0xfff) || NumBytes == 0) {
BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg)
.addReg(SrcReg, RegState::Kill)
.addImm(NumBytes & 0xfff)
.setMIFlag(MIFlags);
// Next update should use the register we've just defined.
SrcReg = DstReg;
}
if (NumBytes & 0xfff000) {
BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg)
.addReg(SrcReg, RegState::Kill)
.addImm(NumBytes >> 12)
.setMIFlag(MIFlags);
}
}
void llvm::emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
DebugLoc dl, const TargetInstrInfo &TII,
unsigned ScratchReg, int64_t NumBytes,
MachineInstr::MIFlag MIFlags) {
emitRegUpdate(MBB, MI, dl, TII, AArch64::XSP, AArch64::XSP, AArch64::X16,
NumBytes, MIFlags);
}
namespace {
struct LDTLSCleanup : public MachineFunctionPass {
static char ID;
LDTLSCleanup() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
AArch64MachineFunctionInfo* MFI
= MF.getInfo<AArch64MachineFunctionInfo>();
if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
// No point folding accesses if there isn't at least two.
return false;
}
MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
return VisitNode(DT->getRootNode(), 0);
}
// Visit the dominator subtree rooted at Node in pre-order.
// If TLSBaseAddrReg is non-null, then use that to replace any
// TLS_base_addr instructions. Otherwise, create the register
// when the first such instruction is seen, and then use it
// as we encounter more instructions.
bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
MachineBasicBlock *BB = Node->getBlock();
bool Changed = false;
// Traverse the current block.
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
++I) {
switch (I->getOpcode()) {
case AArch64::TLSDESC_BLRx:
// Make sure it's a local dynamic access.
if (!I->getOperand(1).isSymbol() ||
strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
break;
if (TLSBaseAddrReg)
I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
else
I = SetRegister(I, &TLSBaseAddrReg);
Changed = true;
break;
default:
break;
}
}
// Visit the children of this block in the dominator tree.
for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
I != E; ++I) {
Changed |= VisitNode(*I, TLSBaseAddrReg);
}
return Changed;
}
// Replace the TLS_base_addr instruction I with a copy from
// TLSBaseAddrReg, returning the new instruction.
MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
unsigned TLSBaseAddrReg) {
MachineFunction *MF = I->getParent()->getParent();
const AArch64TargetMachine *TM =
static_cast<const AArch64TargetMachine *>(&MF->getTarget());
const AArch64InstrInfo *TII = TM->getInstrInfo();
// Insert a Copy from TLSBaseAddrReg to x0, which is where the rest of the
// code sequence assumes the address will be.
MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
TII->get(TargetOpcode::COPY),
AArch64::X0)
.addReg(TLSBaseAddrReg);
// Erase the TLS_base_addr instruction.
I->eraseFromParent();
return Copy;
}
// Create a virtal register in *TLSBaseAddrReg, and populate it by
// inserting a copy instruction after I. Returns the new instruction.
MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
MachineFunction *MF = I->getParent()->getParent();
const AArch64TargetMachine *TM =
static_cast<const AArch64TargetMachine *>(&MF->getTarget());
const AArch64InstrInfo *TII = TM->getInstrInfo();
// Create a virtual register for the TLS base address.
MachineRegisterInfo &RegInfo = MF->getRegInfo();
*TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
// Insert a copy from X0 to TLSBaseAddrReg for later.
MachineInstr *Next = I->getNextNode();
MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
TII->get(TargetOpcode::COPY),
*TLSBaseAddrReg)
.addReg(AArch64::X0);
return Copy;
}
const char *getPassName() const override {
return "Local Dynamic TLS Access Clean-up";
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
}
char LDTLSCleanup::ID = 0;
FunctionPass*
llvm::createAArch64CleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }

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//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64INSTRINFO_H
#define LLVM_TARGET_AARCH64INSTRINFO_H
#include "AArch64RegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "AArch64GenInstrInfo.inc"
namespace llvm {
class AArch64Subtarget;
class AArch64InstrInfo : public AArch64GenInstrInfo {
const AArch64RegisterInfo RI;
const AArch64Subtarget &Subtarget;
public:
explicit AArch64InstrInfo(const AArch64Subtarget &TM);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
const TargetRegisterInfo &getRegisterInfo() const { return RI; }
const AArch64Subtarget &getSubTarget() const { return Subtarget; }
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
void CopyPhysRegTuple(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg) const;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
/// Look through the instructions in this function and work out the largest
/// the stack frame can be while maintaining the ability to address local
/// slots with no complexities.
unsigned estimateRSStackLimit(MachineFunction &MF) const;
/// getAddressConstraints - For loads and stores (and PRFMs) taking an
/// immediate offset, this function determines the constraints required for
/// the immediate. It must satisfy:
/// + MinOffset <= imm <= MaxOffset
/// + imm % OffsetScale == 0
void getAddressConstraints(const MachineInstr &MI, int &AccessScale,
int &MinOffset, int &MaxOffset) const;
unsigned getInstSizeInBytes(const MachineInstr &MI) const;
unsigned getInstBundleLength(const MachineInstr &MI) const;
};
bool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
unsigned FrameReg, int &Offset,
const AArch64InstrInfo &TII);
void emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
DebugLoc dl, const TargetInstrInfo &TII,
unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
int64_t NumBytes,
MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
DebugLoc dl, const TargetInstrInfo &TII,
unsigned ScratchReg, int64_t NumBytes,
MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
}
#endif

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//===-- AArch64MCInstLower.cpp - Convert AArch64 MachineInstr to an MCInst -==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains code to lower AArch64 MachineInstrs to their corresponding
// MCInst records.
//
//===----------------------------------------------------------------------===//
#include "AArch64AsmPrinter.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64MCExpr.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
using namespace llvm;
MCOperand
AArch64AsmPrinter::lowerSymbolOperand(const MachineOperand &MO,
const MCSymbol *Sym) const {
const MCExpr *Expr = nullptr;
Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, OutContext);
switch (MO.getTargetFlags()) {
case AArch64II::MO_GOT:
Expr = AArch64MCExpr::CreateGOT(Expr, OutContext);
break;
case AArch64II::MO_GOT_LO12:
Expr = AArch64MCExpr::CreateGOTLo12(Expr, OutContext);
break;
case AArch64II::MO_LO12:
Expr = AArch64MCExpr::CreateLo12(Expr, OutContext);
break;
case AArch64II::MO_DTPREL_G1:
Expr = AArch64MCExpr::CreateDTPREL_G1(Expr, OutContext);
break;
case AArch64II::MO_DTPREL_G0_NC:
Expr = AArch64MCExpr::CreateDTPREL_G0_NC(Expr, OutContext);
break;
case AArch64II::MO_GOTTPREL:
Expr = AArch64MCExpr::CreateGOTTPREL(Expr, OutContext);
break;
case AArch64II::MO_GOTTPREL_LO12:
Expr = AArch64MCExpr::CreateGOTTPRELLo12(Expr, OutContext);
break;
case AArch64II::MO_TLSDESC:
Expr = AArch64MCExpr::CreateTLSDesc(Expr, OutContext);
break;
case AArch64II::MO_TLSDESC_LO12:
Expr = AArch64MCExpr::CreateTLSDescLo12(Expr, OutContext);
break;
case AArch64II::MO_TPREL_G1:
Expr = AArch64MCExpr::CreateTPREL_G1(Expr, OutContext);
break;
case AArch64II::MO_TPREL_G0_NC:
Expr = AArch64MCExpr::CreateTPREL_G0_NC(Expr, OutContext);
break;
case AArch64II::MO_ABS_G3:
Expr = AArch64MCExpr::CreateABS_G3(Expr, OutContext);
break;
case AArch64II::MO_ABS_G2_NC:
Expr = AArch64MCExpr::CreateABS_G2_NC(Expr, OutContext);
break;
case AArch64II::MO_ABS_G1_NC:
Expr = AArch64MCExpr::CreateABS_G1_NC(Expr, OutContext);
break;
case AArch64II::MO_ABS_G0_NC:
Expr = AArch64MCExpr::CreateABS_G0_NC(Expr, OutContext);
break;
case AArch64II::MO_NO_FLAG:
// Expr is already correct
break;
default:
llvm_unreachable("Unexpected MachineOperand flag");
}
if (!MO.isJTI() && MO.getOffset())
Expr = MCBinaryExpr::CreateAdd(Expr,
MCConstantExpr::Create(MO.getOffset(),
OutContext),
OutContext);
return MCOperand::CreateExpr(Expr);
}
bool AArch64AsmPrinter::lowerOperand(const MachineOperand &MO,
MCOperand &MCOp) const {
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
if (MO.isImplicit())
return false;
assert(!MO.getSubReg() && "Subregs should be eliminated!");
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
MCOp = MCOperand::CreateImm(MO.getImm());
break;
case MachineOperand::MO_FPImmediate: {
assert(MO.getFPImm()->isZero() && "Only fp imm 0.0 is supported");
MCOp = MCOperand::CreateFPImm(0.0);
break;
}
case MachineOperand::MO_BlockAddress:
MCOp = lowerSymbolOperand(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
break;
case MachineOperand::MO_ExternalSymbol:
MCOp = lowerSymbolOperand(MO, GetExternalSymbolSymbol(MO.getSymbolName()));
break;
case MachineOperand::MO_GlobalAddress:
MCOp = lowerSymbolOperand(MO, getSymbol(MO.getGlobal()));
break;
case MachineOperand::MO_MachineBasicBlock:
MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), OutContext));
break;
case MachineOperand::MO_JumpTableIndex:
MCOp = lowerSymbolOperand(MO, GetJTISymbol(MO.getIndex()));
break;
case MachineOperand::MO_ConstantPoolIndex:
MCOp = lowerSymbolOperand(MO, GetCPISymbol(MO.getIndex()));
break;
case MachineOperand::MO_RegisterMask:
// Ignore call clobbers
return false;
}
return true;
}
void llvm::LowerAArch64MachineInstrToMCInst(const MachineInstr *MI,
MCInst &OutMI,
AArch64AsmPrinter &AP) {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
if (AP.lowerOperand(MO, MCOp))
OutMI.addOperand(MCOp);
}
}

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lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
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//===-- AArch64MachineFuctionInfo.cpp - AArch64 machine function info -----===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file just contains the anchor for the AArch64MachineFunctionInfo to
// force vtable emission.
//
//===----------------------------------------------------------------------===//
#include "AArch64MachineFunctionInfo.h"
using namespace llvm;
void AArch64MachineFunctionInfo::anchor() { }

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lib/Target/AArch64/AArch64MachineFunctionInfo.h
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//=- AArch64MachineFuctionInfo.h - AArch64 machine function info -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares AArch64-specific per-machine-function information.
//
//===----------------------------------------------------------------------===//
#ifndef AARCH64MACHINEFUNCTIONINFO_H
#define AARCH64MACHINEFUNCTIONINFO_H
#include "llvm/CodeGen/MachineFunction.h"
namespace llvm {
/// This class is derived from MachineFunctionInfo and contains private AArch64
/// target-specific information for each MachineFunction.
class AArch64MachineFunctionInfo : public MachineFunctionInfo {
virtual void anchor();
/// Number of bytes of arguments this function has on the stack. If the callee
/// is expected to restore the argument stack this should be a multiple of 16,
/// all usable during a tail call.
///
/// The alternative would forbid tail call optimisation in some cases: if we
/// want to transfer control from a function with 8-bytes of stack-argument
/// space to a function with 16-bytes then misalignment of this value would
/// make a stack adjustment necessary, which could not be undone by the
/// callee.
unsigned BytesInStackArgArea;
/// The number of bytes to restore to deallocate space for incoming
/// arguments. Canonically 0 in the C calling convention, but non-zero when
/// callee is expected to pop the args.
unsigned ArgumentStackToRestore;
/// If the stack needs to be adjusted on frame entry in two stages, this
/// records the size of the first adjustment just prior to storing
/// callee-saved registers. The callee-saved slots are addressed assuming
/// SP == <incoming-SP> - InitialStackAdjust.
unsigned InitialStackAdjust;
/// Number of local-dynamic TLS accesses.
unsigned NumLocalDynamics;
/// @see AArch64 Procedure Call Standard, B.3
///
/// The Frame index of the area where LowerFormalArguments puts the
/// general-purpose registers that might contain variadic parameters.
int VariadicGPRIdx;
/// @see AArch64 Procedure Call Standard, B.3
///
/// The size of the frame object used to store the general-purpose registers
/// which might contain variadic arguments. This is the offset from
/// VariadicGPRIdx to what's stored in __gr_top.
unsigned VariadicGPRSize;
/// @see AArch64 Procedure Call Standard, B.3
///
/// The Frame index of the area where LowerFormalArguments puts the
/// floating-point registers that might contain variadic parameters.
int VariadicFPRIdx;
/// @see AArch64 Procedure Call Standard, B.3
///
/// The size of the frame object used to store the floating-point registers
/// which might contain variadic arguments. This is the offset from
/// VariadicFPRIdx to what's stored in __vr_top.
unsigned VariadicFPRSize;
/// @see AArch64 Procedure Call Standard, B.3
///
/// The Frame index of an object pointing just past the last known stacked
/// argument on entry to a variadic function. This goes into the __stack field
/// of the va_list type.
int VariadicStackIdx;
/// The offset of the frame pointer from the stack pointer on function
/// entry. This is expected to be negative.
int FramePointerOffset;
public:
AArch64MachineFunctionInfo()
: BytesInStackArgArea(0),
ArgumentStackToRestore(0),
InitialStackAdjust(0),
NumLocalDynamics(0),
VariadicGPRIdx(0),
VariadicGPRSize(0),
VariadicFPRIdx(0),
VariadicFPRSize(0),
VariadicStackIdx(0),
FramePointerOffset(0) {}
explicit AArch64MachineFunctionInfo(MachineFunction &MF)
: BytesInStackArgArea(0),
ArgumentStackToRestore(0),
InitialStackAdjust(0),
NumLocalDynamics(0),
VariadicGPRIdx(0),
VariadicGPRSize(0),
VariadicFPRIdx(0),
VariadicFPRSize(0),
VariadicStackIdx(0),
FramePointerOffset(0) {}
unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; }
void setBytesInStackArgArea (unsigned bytes) { BytesInStackArgArea = bytes;}
unsigned getArgumentStackToRestore() const { return ArgumentStackToRestore; }
void setArgumentStackToRestore(unsigned bytes) {
ArgumentStackToRestore = bytes;
}
unsigned getInitialStackAdjust() const { return InitialStackAdjust; }
void setInitialStackAdjust(unsigned bytes) { InitialStackAdjust = bytes; }
unsigned getNumLocalDynamicTLSAccesses() const { return NumLocalDynamics; }
void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamics; }
int getVariadicGPRIdx() const { return VariadicGPRIdx; }
void setVariadicGPRIdx(int Idx) { VariadicGPRIdx = Idx; }
unsigned getVariadicGPRSize() const { return VariadicGPRSize; }
void setVariadicGPRSize(unsigned Size) { VariadicGPRSize = Size; }
int getVariadicFPRIdx() const { return VariadicFPRIdx; }
void setVariadicFPRIdx(int Idx) { VariadicFPRIdx = Idx; }
unsigned getVariadicFPRSize() const { return VariadicFPRSize; }
void setVariadicFPRSize(unsigned Size) { VariadicFPRSize = Size; }
int getVariadicStackIdx() const { return VariadicStackIdx; }
void setVariadicStackIdx(int Idx) { VariadicStackIdx = Idx; }
int getFramePointerOffset() const { return FramePointerOffset; }
void setFramePointerOffset(int Idx) { FramePointerOffset = Idx; }
};
} // End llvm namespace
#endif

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//===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 implementation of the TargetRegisterInfo
// class.
//
//===----------------------------------------------------------------------===//
#include "AArch64RegisterInfo.h"
#include "AArch64FrameLowering.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
using namespace llvm;
#define GET_REGINFO_TARGET_DESC
#include "AArch64GenRegisterInfo.inc"
AArch64RegisterInfo::AArch64RegisterInfo()
: AArch64GenRegisterInfo(AArch64::X30) {
}
const MCPhysReg *
AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
return CSR_PCS_SaveList;
}
const uint32_t*
AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID) const {
return CSR_PCS_RegMask;
}
const uint32_t *AArch64RegisterInfo::getTLSDescCallPreservedMask() const {
return TLSDesc_RegMask;
}
const TargetRegisterClass *
AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
if (RC == &AArch64::FlagClassRegClass)
return &AArch64::GPR64RegClass;
return RC;
}
BitVector
AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
Reserved.set(AArch64::XSP);
Reserved.set(AArch64::WSP);
Reserved.set(AArch64::XZR);
Reserved.set(AArch64::WZR);
if (TFI->hasFP(MF)) {
Reserved.set(AArch64::X29);
Reserved.set(AArch64::W29);
}
return Reserved;
}
static bool hasFrameOffset(int opcode) {
return opcode != AArch64::LD1x2_8B && opcode != AArch64::LD1x3_8B &&
opcode != AArch64::LD1x4_8B && opcode != AArch64::ST1x2_8B &&
opcode != AArch64::ST1x3_8B && opcode != AArch64::ST1x4_8B &&
opcode != AArch64::LD1x2_16B && opcode != AArch64::LD1x3_16B &&
opcode != AArch64::LD1x4_16B && opcode != AArch64::ST1x2_16B &&
opcode != AArch64::ST1x3_16B && opcode != AArch64::ST1x4_16B;
}
void
AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const {
assert(SPAdj == 0 && "Cannot deal with nonzero SPAdj yet");
MachineInstr &MI = *MBBI;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo *MFI = MF.getFrameInfo();
const AArch64FrameLowering *TFI =
static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering());
// In order to work out the base and offset for addressing, the FrameLowering
// code needs to know (sometimes) whether the instruction is storing/loading a
// callee-saved register, or whether it's a more generic
// operation. Fortunately the frame indices are used *only* for that purpose
// and are contiguous, so we can check here.
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
int MinCSFI = 0;
int MaxCSFI = -1;
if (CSI.size()) {
MinCSFI = CSI[0].getFrameIdx();
MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
}
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
bool IsCalleeSaveOp = FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI;
unsigned FrameReg;
int64_t Offset;
Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
IsCalleeSaveOp);
// A vector load/store instruction doesn't have an offset operand.
bool HasOffsetOp = hasFrameOffset(MI.getOpcode());
if (HasOffsetOp)
Offset += MI.getOperand(FIOperandNum + 1).getImm();
// DBG_VALUE instructions have no real restrictions so they can be handled
// easily.
if (MI.isDebugValue()) {
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false);
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
return;
}
const AArch64InstrInfo &TII =
*static_cast<const AArch64InstrInfo*>(MF.getTarget().getInstrInfo());
int MinOffset, MaxOffset, OffsetScale;
if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s || !HasOffsetOp) {
MinOffset = 0;
MaxOffset = 0xfff;
OffsetScale = 1;
} else {
// Load/store of a stack object
TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
}
// There are two situations we don't use frame + offset directly in the
// instruction:
// (1) The offset can't really be scaled
// (2) Can't encode offset as it doesn't have an offset operand
if ((Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) ||
(!HasOffsetOp && Offset != 0)) {
unsigned BaseReg =
MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
BaseReg, FrameReg, BaseReg, Offset);
FrameReg = BaseReg;
Offset = 0;
}
// Negative offsets are expected if we address from FP, but for
// now this checks nothing has gone horribly wrong.
assert(Offset >= 0 && "Unexpected negative offset from SP");
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
if (HasOffsetOp)
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale);
}
unsigned
AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
if (TFI->hasFP(MF))
return AArch64::X29;
else
return AArch64::XSP;
}
bool
AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
const AArch64FrameLowering *AFI
= static_cast<const AArch64FrameLowering*>(TFI);
return AFI->useFPForAddressing(MF);
}

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//==- AArch64RegisterInfo.h - AArch64 Register Information Impl -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 implementation of the MCRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64REGISTERINFO_H
#define LLVM_TARGET_AARCH64REGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "AArch64GenRegisterInfo.inc"
namespace llvm {
class AArch64InstrInfo;
class AArch64Subtarget;
struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
AArch64RegisterInfo();
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
unsigned getCSRFirstUseCost() const override {
// The cost will be compared against BlockFrequency where entry has the
// value of 1 << 14. A value of 5 will choose to spill or split really
// cold path instead of using a callee-saved register.
return 5;
}
const uint32_t *getTLSDescCallPreservedMask() const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
unsigned getFrameRegister(const MachineFunction &MF) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
RegScavenger *Rs = nullptr) const override;
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns original class if it is
/// possible to copy between a two registers of the specified class.
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
/// getLargestLegalSuperClass - Returns the largest super class of RC that is
/// legal to use in the current sub-target and has the same spill size.
const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override {
if (RC == &AArch64::tcGPR64RegClass)
return &AArch64::GPR64RegClass;
return RC;
}
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
}
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
return true;
}
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
};
} // end namespace llvm
#endif // LLVM_TARGET_AARCH64REGISTERINFO_H

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//===- AArch64RegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains declarations that describe the AArch64 register file
//
//===----------------------------------------------------------------------===//
let Namespace = "AArch64" in {
def sub_128 : SubRegIndex<128>;
def sub_64 : SubRegIndex<64>;
def sub_32 : SubRegIndex<32>;
def sub_16 : SubRegIndex<16>;
def sub_8 : SubRegIndex<8>;
// Note: Code depends on these having consecutive numbers.
def qqsub : SubRegIndex<256, 256>;
def qsub_0 : SubRegIndex<128>;
def qsub_1 : SubRegIndex<128, 128>;
def qsub_2 : ComposedSubRegIndex<qqsub, qsub_0>;
def qsub_3 : ComposedSubRegIndex<qqsub, qsub_1>;
def dsub_0 : SubRegIndex<64>;
def dsub_1 : SubRegIndex<64, 64>;
def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
}
// Registers are identified with 5-bit ID numbers.
class AArch64Reg<bits<16> enc, string n> : Register<n> {
let HWEncoding = enc;
let Namespace = "AArch64";
}
class AArch64RegWithSubs<bits<16> enc, string n, list<Register> subregs = [],
list<SubRegIndex> inds = []>
: AArch64Reg<enc, n> {
let SubRegs = subregs;
let SubRegIndices = inds;
}
//===----------------------------------------------------------------------===//
// Integer registers: w0-w30, wzr, wsp, x0-x30, xzr, sp
//===----------------------------------------------------------------------===//
foreach Index = 0-30 in {
def W#Index : AArch64Reg< Index, "w"#Index>, DwarfRegNum<[Index]>;
}
def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
def WZR : AArch64Reg<31, "wzr">;
// Could be combined with previous loop, but this way leaves w and x registers
// consecutive as LLVM register numbers, which makes for easier debugging.
foreach Index = 0-30 in {
def X#Index : AArch64RegWithSubs<Index, "x"#Index,
[!cast<Register>("W"#Index)], [sub_32]>,
DwarfRegNum<[Index]>;
}
def XSP : AArch64RegWithSubs<31, "sp", [WSP], [sub_32]>, DwarfRegNum<[31]>;
def XZR : AArch64RegWithSubs<31, "xzr", [WZR], [sub_32]>;
// Most instructions treat register 31 as zero for reads and a black-hole for
// writes.
// Note that the order of registers is important for the Disassembler here:
// tablegen uses it to form MCRegisterClass::getRegister, which we assume can
// take an encoding value.
def GPR32 : RegisterClass<"AArch64", [i32], 32,
(add (sequence "W%u", 0, 30), WZR)> {
}
def GPR64 : RegisterClass<"AArch64", [i64], 64,
(add (sequence "X%u", 0, 30), XZR)> {
}
def GPR32nowzr : RegisterClass<"AArch64", [i32], 32,
(sequence "W%u", 0, 30)> {
}
def GPR64noxzr : RegisterClass<"AArch64", [i64], 64,
(sequence "X%u", 0, 30)> {
}
// For tail calls, we can't use callee-saved registers or the structure-return
// register, as they are supposed to be live across function calls and may be
// clobbered by the epilogue.
def tcGPR64 : RegisterClass<"AArch64", [i64], 64,
(add (sequence "X%u", 0, 7),
(sequence "X%u", 9, 18))> {
}
// Certain addressing-useful instructions accept sp directly. Again the order of
// registers is important to the Disassembler.
def GPR32wsp : RegisterClass<"AArch64", [i32], 32,
(add (sequence "W%u", 0, 30), WSP)> {
}
def GPR64xsp : RegisterClass<"AArch64", [i64], 64,
(add (sequence "X%u", 0, 30), XSP)> {
}
// Some aliases *only* apply to SP (e.g. MOV uses different encoding for SP and
// non-SP variants). We can't use a bare register in those patterns because
// TableGen doesn't like it, so we need a class containing just stack registers
def Rxsp : RegisterClass<"AArch64", [i64], 64,
(add XSP)> {
}
def Rwsp : RegisterClass<"AArch64", [i32], 32,
(add WSP)> {
}
//===----------------------------------------------------------------------===//
// Scalar registers in the vector unit:
// b0-b31, h0-h31, s0-s31, d0-d31, q0-q31
//===----------------------------------------------------------------------===//
foreach Index = 0-31 in {
def B # Index : AArch64Reg< Index, "b" # Index>,
DwarfRegNum<[!add(Index, 64)]>;
def H # Index : AArch64RegWithSubs<Index, "h" # Index,
[!cast<Register>("B" # Index)], [sub_8]>,
DwarfRegNum<[!add(Index, 64)]>;
def S # Index : AArch64RegWithSubs<Index, "s" # Index,
[!cast<Register>("H" # Index)], [sub_16]>,
DwarfRegNum<[!add(Index, 64)]>;
def D # Index : AArch64RegWithSubs<Index, "d" # Index,
[!cast<Register>("S" # Index)], [sub_32]>,
DwarfRegNum<[!add(Index, 64)]>;
def Q # Index : AArch64RegWithSubs<Index, "q" # Index,
[!cast<Register>("D" # Index)], [sub_64]>,
DwarfRegNum<[!add(Index, 64)]>;
}
def FPR8 : RegisterClass<"AArch64", [v1i8], 8,
(sequence "B%u", 0, 31)> {
}
def FPR16 : RegisterClass<"AArch64", [f16, v1i16], 16,
(sequence "H%u", 0, 31)> {
}
def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
(sequence "S%u", 0, 31)> {
}
def FPR64 : RegisterClass<"AArch64",
[f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
64, (sequence "D%u", 0, 31)>;
def FPR128 : RegisterClass<"AArch64",
[f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 31)>;
def FPR64Lo : RegisterClass<"AArch64",
[f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
64, (sequence "D%u", 0, 15)>;
def FPR128Lo : RegisterClass<"AArch64",
[f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
128, (sequence "Q%u", 0, 15)>;
//===----------------------------------------------------------------------===//
// Vector registers:
//===----------------------------------------------------------------------===//
def VPR64AsmOperand : AsmOperandClass {
let Name = "VPR";
let PredicateMethod = "isReg";
let RenderMethod = "addRegOperands";
}
def VPR64 : RegisterOperand<FPR64, "printVPRRegister">;
def VPR128 : RegisterOperand<FPR128, "printVPRRegister">;
def VPR64Lo : RegisterOperand<FPR64Lo, "printVPRRegister">;
def VPR128Lo : RegisterOperand<FPR128Lo, "printVPRRegister">;
// Flags register
def NZCV : Register<"nzcv"> {
let Namespace = "AArch64";
}
def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
let CopyCost = -1;
let isAllocatable = 0;
}
//===----------------------------------------------------------------------===//
// Consecutive vector registers
//===----------------------------------------------------------------------===//
// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0
def Tuples2D : RegisterTuples<[dsub_0, dsub_1],
[(rotl FPR64, 0), (rotl FPR64, 1)]>;
// 3 Consecutive 64-bit registers: D0_D1_D2, ..., D31_D0_D1
def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
[(rotl FPR64, 0), (rotl FPR64, 1),
(rotl FPR64, 2)]>;
// 4 Consecutive 64-bit registers: D0_D1_D2_D3, ..., D31_D0_D1_D2
def Tuples4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],
[(rotl FPR64, 0), (rotl FPR64, 1),
(rotl FPR64, 2), (rotl FPR64, 3)]>;
// 2 Consecutive 128-bit registers: Q0_Q1, Q1_Q2, ..., Q30_Q31
def Tuples2Q : RegisterTuples<[qsub_0, qsub_1],
[(rotl FPR128, 0), (rotl FPR128, 1)]>;
// 3 Consecutive 128-bit registers: Q0_Q1_Q2, ..., Q31_Q0_Q1
def Tuples3Q : RegisterTuples<[qsub_0, qsub_1, qsub_2],
[(rotl FPR128, 0), (rotl FPR128, 1),
(rotl FPR128, 2)]>;
// 4 Consecutive 128-bit registers: Q0_Q1_Q2_Q3, ..., Q31_Q0_Q1_Q2
def Tuples4Q : RegisterTuples<[qsub_0, qsub_1, qsub_2, qsub_3],
[(rotl FPR128, 0), (rotl FPR128, 1),
(rotl FPR128, 2), (rotl FPR128, 3)]>;
// The followings are super register classes to model 2/3/4 consecutive
// 64-bit/128-bit registers.
def DPair : RegisterClass<"AArch64", [v2i64], 64, (add Tuples2D)>;
def DTriple : RegisterClass<"AArch64", [untyped], 64, (add Tuples3D)> {
let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
}
def DQuad : RegisterClass<"AArch64", [v4i64], 64, (add Tuples4D)>;
def QPair : RegisterClass<"AArch64", [v4i64], 128, (add Tuples2Q)>;
def QTriple : RegisterClass<"AArch64", [untyped], 128, (add Tuples3Q)> {
let Size = 384; // 3 x 128 bits, we have no predefined type of that size.
}
def QQuad : RegisterClass<"AArch64", [v8i64], 128, (add Tuples4Q)>;
// The followings are vector list operands
multiclass VectorList_operands<string PREFIX, string LAYOUT, int Count,
RegisterClass RegList> {
def _asmoperand : AsmOperandClass {
let Name = PREFIX # LAYOUT # Count;
let RenderMethod = "addVectorListOperands";
let PredicateMethod =
"isVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">";
let ParserMethod = "ParseVectorList";
}
def _operand : RegisterOperand<RegList,
"printVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">"> {
let ParserMatchClass =
!cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand");
}
}
multiclass VectorList_BHSD<string PREFIX, int Count, RegisterClass DRegList,
RegisterClass QRegList> {
defm 8B : VectorList_operands<PREFIX, "8B", Count, DRegList>;
defm 4H : VectorList_operands<PREFIX, "4H", Count, DRegList>;
defm 2S : VectorList_operands<PREFIX, "2S", Count, DRegList>;
defm 1D : VectorList_operands<PREFIX, "1D", Count, DRegList>;
defm 16B : VectorList_operands<PREFIX, "16B", Count, QRegList>;
defm 8H : VectorList_operands<PREFIX, "8H", Count, QRegList>;
defm 4S : VectorList_operands<PREFIX, "4S", Count, QRegList>;
defm 2D : VectorList_operands<PREFIX, "2D", Count, QRegList>;
}
// Vector list operand with 1/2/3/4 registers: VOne8B_operand,..., VQuad2D_operand
defm VOne : VectorList_BHSD<"VOne", 1, FPR64, FPR128>;
defm VPair : VectorList_BHSD<"VPair", 2, DPair, QPair>;
defm VTriple : VectorList_BHSD<"VTriple", 3, DTriple, QTriple>;
defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;

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//===- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Generic processor itineraries for legacy compatibility.
def GenericItineraries : ProcessorItineraries<[], [], []>;
//===----------------------------------------------------------------------===//
// Base SchedReadWrite types
// Basic ALU
def WriteALU : SchedWrite; // Generic: may contain shift and/or ALU operation
def WriteALUs : SchedWrite; // Shift only with no ALU operation
def ReadALU : SchedRead; // Operand not needed for shifting
def ReadALUs : SchedRead; // Operand needed for shifting
// Multiply with optional accumulate
def WriteMAC : SchedWrite;
def ReadMAC : SchedRead;
// Compares
def WriteCMP : SchedWrite;
def ReadCMP : SchedRead;
// Division
def WriteDiv : SchedWrite;
def ReadDiv : SchedRead;
// Loads
def WriteLd : SchedWrite;
def WritePreLd : SchedWrite;
def WriteVecLd : SchedWrite;
def ReadLd : SchedRead;
def ReadPreLd : SchedRead;
def ReadVecLd : SchedRead;
// Stores
def WriteSt : SchedWrite;
def WriteVecSt : SchedWrite;
def ReadSt : SchedRead;
def ReadVecSt : SchedRead;
// Branches
def WriteBr : SchedWrite;
def WriteBrL : SchedWrite;
def ReadBr : SchedRead;
// Floating Point ALU
def WriteFPALU : SchedWrite;
def ReadFPALU : SchedRead;
// Floating Point MAC, Mul, Div, Sqrt
// Most processors will simply send all of these down a dedicated pipe, but
// they're explicitly separated here for flexibility of modeling later. May
// consider consolidating them into a single WriteFPXXXX type in the future.
def WriteFPMAC : SchedWrite;
def WriteFPMul : SchedWrite;
def WriteFPDiv : SchedWrite;
def WriteFPSqrt : SchedWrite;
def ReadFPMAC : SchedRead;
def ReadFPMul : SchedRead;
def ReadFPDiv : SchedRead;
def ReadFPSqrt : SchedRead;
// Noop
def WriteNoop : SchedWrite;
//===----------------------------------------------------------------------===//
// Subtarget specific Machine Models.
include "AArch64ScheduleA53.td"

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//=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the ARM Cortex A53 processors.
//
//===----------------------------------------------------------------------===//
// ===---------------------------------------------------------------------===//
// The following definitions describe the simpler per-operand machine model.
// This works with MachineScheduler. See MCSchedModel.h for details.
// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
def CortexA53Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 2; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
// Specification - Instruction Timings"
// v 1.0 Spreadsheet
}
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available.
// Modeling each pipeline as a ProcResource using the default BufferSize = -1.
// Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
// current configuration performs better with the basic latencies provided so
// far. Will revisit BufferSize once the latency information is more accurate.
let SchedModel = CortexA53Model in {
def A53UnitALU : ProcResource<2>; // Int ALU
def A53UnitMAC : ProcResource<1>; // Int MAC
def A53UnitDiv : ProcResource<1>; // Int Division
def A53UnitLdSt : ProcResource<1>; // Load/Store
def A53UnitB : ProcResource<1>; // Branch
def A53UnitFPALU : ProcResource<1>; // FP ALU
def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedWrite types which both map the ProcResources and
// set the latency.
// Issue - Every instruction must consume an A53WriteIssue. Optionally,
// instructions that cannot be dual-issued will also include the
// A53WriteIssue2nd in their SchedRW list. That second WriteRes will
// ensure that a second issue slot is consumed.
def A53WriteIssue : SchedWriteRes<[]>;
def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
// ALU - These are reduced to 1 despite a true latency of 4 in order to easily
// model forwarding logic. Once forwarding is properly modelled, then
// they'll be corrected.
def : WriteRes<WriteALU, [A53UnitALU]> { let Latency = 1; }
def : WriteRes<WriteALUs, [A53UnitALU]> { let Latency = 1; }
def : WriteRes<WriteCMP, [A53UnitALU]> { let Latency = 1; }
// MAC
def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }
// Div
def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }
// Load - Note: Vector loads take 1-5 cycles to issue. For the WriteVecLd below,
// choosing the median of 3 which makes the latency 6. May model this more
// carefully in the future.
def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }
def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }
def : WriteRes<WriteVecLd, [A53UnitLdSt]> { let Latency = 6; }
// Store - Note: Vector stores take 1-3 cycles to issue. For the ReadVecSt below,
// choosing the median of 2 which makes the latency 5. May model this more
// carefully in the future.
def : WriteRes<WriteSt, [A53UnitLdSt]> { let Latency = 4; }
def : WriteRes<WriteVecSt, [A53UnitLdSt]> { let Latency = 5; }
// Branch
def : WriteRes<WriteBr, [A53UnitB]>;
def : WriteRes<WriteBrL, [A53UnitB]>;
// FP ALU
def : WriteRes<WriteFPALU, [A53UnitFPALU]> {let Latency = 6; }
// FP MAC, Mul, Div, Sqrt
// Using Double Precision numbers for now as a worst case. Additionally, not
// modeling the exact hazard but instead treating the whole pipe as a hazard.
// As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
// have a total latency of 33 and 32 respectively but only a hazard of 29 and
// 28 (double-prescion example).
def : WriteRes<WriteFPMAC, [A53UnitFPMDS]> { let Latency = 10; }
def : WriteRes<WriteFPMul, [A53UnitFPMDS]> { let Latency = 6; }
def : WriteRes<WriteFPDiv, [A53UnitFPMDS]> { let Latency = 33;
let ResourceCycles = [29]; }
def : WriteRes<WriteFPSqrt, [A53UnitFPMDS]> { let Latency = 32;
let ResourceCycles = [28]; }
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.
// No forwarding defined for ReadALU yet.
def : ReadAdvance<ReadALU, 0>;
// No forwarding defined for ReadCMP yet.
def : ReadAdvance<ReadCMP, 0>;
// No forwarding defined for ReadBr yet.
def : ReadAdvance<ReadBr, 0>;
// No forwarding defined for ReadMAC yet.
def : ReadAdvance<ReadMAC, 0>;
// No forwarding defined for ReadDiv yet.
def : ReadAdvance<ReadDiv, 0>;
// No forwarding defined for ReadLd, ReadPreLd, ReadVecLd yet.
def : ReadAdvance<ReadLd, 0>;
def : ReadAdvance<ReadPreLd, 0>;
def : ReadAdvance<ReadVecLd, 0>;
// No forwarding defined for ReadSt and ReadVecSt yet.
def : ReadAdvance<ReadSt, 0>;
def : ReadAdvance<ReadVecSt, 0>;
// No forwarding defined for ReadFPALU yet.
def : ReadAdvance<ReadFPALU, 0>;
// No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
def : ReadAdvance<ReadFPMAC, 0>;
def : ReadAdvance<ReadFPMul, 0>;
def : ReadAdvance<ReadFPDiv, 0>;
def : ReadAdvance<ReadFPSqrt, 0>;
}

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//===-- AArch64SelectionDAGInfo.cpp - AArch64 SelectionDAG Info -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the AArch64SelectionDAGInfo class.
//
//===----------------------------------------------------------------------===//
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/SelectionDAG.h"
using namespace llvm;
#define DEBUG_TYPE "arm-selectiondag-info"
AArch64SelectionDAGInfo::AArch64SelectionDAGInfo(const AArch64TargetMachine &TM)
: TargetSelectionDAGInfo(TM),
Subtarget(&TM.getSubtarget<AArch64Subtarget>()) {
}
AArch64SelectionDAGInfo::~AArch64SelectionDAGInfo() {
}

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lib/Target/AArch64/AArch64SelectionDAGInfo.h
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//===-- AArch64SelectionDAGInfo.h - AArch64 SelectionDAG Info ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the AArch64 subclass for TargetSelectionDAGInfo.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64SELECTIONDAGINFO_H
#define LLVM_AARCH64SELECTIONDAGINFO_H
#include "llvm/Target/TargetSelectionDAGInfo.h"
namespace llvm {
class AArch64TargetMachine;
class AArch64SelectionDAGInfo : public TargetSelectionDAGInfo {
const AArch64Subtarget *Subtarget;
public:
explicit AArch64SelectionDAGInfo(const AArch64TargetMachine &TM);
~AArch64SelectionDAGInfo();
};
}
#endif

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lib/Target/AArch64/AArch64Subtarget.cpp
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//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information --------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the AArch64 specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
#include "AArch64Subtarget.h"
#include "AArch64RegisterInfo.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64-subtarget"
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "AArch64GenSubtargetInfo.inc"
enum AlignMode {
DefaultAlign,
StrictAlign,
NoStrictAlign
};
static cl::opt<AlignMode>
Align(cl::desc("Load/store alignment support"),
cl::Hidden, cl::init(DefaultAlign),
cl::values(
clEnumValN(DefaultAlign, "aarch64-default-align",
"Generate unaligned accesses only on hardware/OS "
"combinations that are known to support them"),
clEnumValN(StrictAlign, "aarch64-strict-align",
"Disallow all unaligned memory accesses"),
clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
"Allow unaligned memory accesses"),
clEnumValEnd));
// Pin the vtable to this file.
void AArch64Subtarget::anchor() {}
AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
bool LittleEndian)
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
HasFPARMv8(false), HasNEON(false), HasCrypto(false), TargetTriple(TT),
CPUString(CPU), IsLittleEndian(LittleEndian) {
initializeSubtargetFeatures(CPU, FS);
}
void AArch64Subtarget::initializeSubtargetFeatures(StringRef CPU,
StringRef FS) {
AllowsUnalignedMem = false;
if (CPU.empty())
CPUString = "generic";
std::string FullFS = FS;
if (CPUString == "generic") {
// Enable FP by default.
if (FullFS.empty())
FullFS = "+fp-armv8";
else
FullFS = "+fp-armv8," + FullFS;
}
ParseSubtargetFeatures(CPU, FullFS);
switch (Align) {
case DefaultAlign:
// Linux targets support unaligned accesses on AARCH64
AllowsUnalignedMem = isTargetLinux();
break;
case StrictAlign:
AllowsUnalignedMem = false;
break;
case NoStrictAlign:
AllowsUnalignedMem = true;
break;
}
}
bool AArch64Subtarget::GVIsIndirectSymbol(const GlobalValue *GV,
Reloc::Model RelocM) const {
if (RelocM == Reloc::Static)
return false;
return !GV->hasLocalLinkage() && !GV->hasHiddenVisibility();
}

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lib/Target/AArch64/AArch64Subtarget.h
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//==-- AArch64Subtarget.h - Define Subtarget for the AArch64 ---*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the AArch64 specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64_SUBTARGET_H
#define LLVM_TARGET_AARCH64_SUBTARGET_H
#include "llvm/ADT/Triple.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
#include "AArch64GenSubtargetInfo.inc"
namespace llvm {
class StringRef;
class GlobalValue;
class AArch64Subtarget : public AArch64GenSubtargetInfo {
virtual void anchor();
protected:
enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
ARMProcFamilyEnum ARMProcFamily;
bool HasFPARMv8;
bool HasNEON;
bool HasCrypto;
/// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
/// accesses for some types. For details, see
/// AArch64TargetLowering::allowsUnalignedMemoryAccesses().
bool AllowsUnalignedMem;
/// TargetTriple - What processor and OS we're targeting.
Triple TargetTriple;
/// CPUString - String name of used CPU.
std::string CPUString;
/// IsLittleEndian - The target is Little Endian
bool IsLittleEndian;
private:
void initializeSubtargetFeatures(StringRef CPU, StringRef FS);
public:
/// This constructor initializes the data members to match that
/// of the specified triple.
///
AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
bool LittleEndian);
bool enableMachineScheduler() const override {
return true;
}
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
bool isLittle() const { return IsLittleEndian; }
const std::string & getCPUString() const { return CPUString; }
};
} // End llvm namespace
#endif // LLVM_TARGET_AARCH64_SUBTARGET_H

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lib/Target/AArch64/AArch64TargetMachine.cpp
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//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the implementation of the AArch64TargetMachine
// methods. Principally just setting up the passes needed to generate correct
// code on this architecture.
//
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/PassManager.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
using namespace llvm;
extern "C" void LLVMInitializeAArch64Target() {
RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
}
AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool LittleEndian)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, LittleEndian),
InstrInfo(Subtarget),
DL(LittleEndian ?
"e-m:e-i64:64-i128:128-n32:64-S128" :
"E-m:e-i64:64-i128:128-n32:64-S128"),
TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();
}
void AArch64leTargetMachine::anchor() { }
AArch64leTargetMachine::
AArch64leTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
void AArch64beTargetMachine::anchor() { }
AArch64beTargetMachine::
AArch64beTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
// Add first the target-independent BasicTTI pass, then our AArch64 pass. This
// allows the AArch64 pass to delegate to the target independent layer when
// appropriate.
PM.add(createBasicTargetTransformInfoPass(this));
PM.add(createAArch64TargetTransformInfoPass(this));
}
namespace {
/// AArch64 Code Generator Pass Configuration Options.
class AArch64PassConfig : public TargetPassConfig {
public:
AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {}
AArch64TargetMachine &getAArch64TargetMachine() const {
return getTM<AArch64TargetMachine>();
}
const AArch64Subtarget &getAArch64Subtarget() const {
return *getAArch64TargetMachine().getSubtargetImpl();
}
bool addPreISel() override;
bool addInstSelector() override;
bool addPreEmitPass() override;
};
} // namespace
bool AArch64PassConfig::addPreISel() {
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createGlobalMergePass(TM));
return false;
}
TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
return new AArch64PassConfig(this, PM);
}
bool AArch64PassConfig::addPreEmitPass() {
addPass(&UnpackMachineBundlesID);
addPass(createAArch64BranchFixupPass());
return true;
}
bool AArch64PassConfig::addInstSelector() {
addPass(createAArch64ISelDAG(getAArch64TargetMachine(), getOptLevel()));
// For ELF, cleanup any local-dynamic TLS accesses.
if (getAArch64Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
addPass(createAArch64CleanupLocalDynamicTLSPass());
return false;
}

94
lib/Target/AArch64/AArch64TargetMachine.h
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//=== AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the AArch64 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64TARGETMACHINE_H
#define LLVM_AARCH64TARGETMACHINE_H
#include "AArch64FrameLowering.h"
#include "AArch64ISelLowering.h"
#include "AArch64InstrInfo.h"
#include "AArch64SelectionDAGInfo.h"
#include "AArch64Subtarget.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class AArch64TargetMachine : public LLVMTargetMachine {
AArch64Subtarget Subtarget;
AArch64InstrInfo InstrInfo;
const DataLayout DL;
AArch64TargetLowering TLInfo;
AArch64SelectionDAGInfo TSInfo;
AArch64FrameLowering FrameLowering;
public:
AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool LittleEndian);
const AArch64InstrInfo *getInstrInfo() const override {
return &InstrInfo;
}
const AArch64FrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
const AArch64TargetLowering *getTargetLowering() const override {
return &TLInfo;
}
const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
const AArch64Subtarget *getSubtargetImpl() const override { return &Subtarget; }
const DataLayout *getDataLayout() const override { return &DL; }
const TargetRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo();
}
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
void addAnalysisPasses(PassManagerBase &PM) override;
};
// AArch64leTargetMachine - AArch64 little endian target machine.
//
class AArch64leTargetMachine : public AArch64TargetMachine {
virtual void anchor();
public:
AArch64leTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};
// AArch64beTargetMachine - AArch64 big endian target machine.
//
class AArch64beTargetMachine : public AArch64TargetMachine {
virtual void anchor();
public:
AArch64beTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
};
} // End llvm namespace
#endif

24
lib/Target/AArch64/AArch64TargetObjectFile.cpp
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@ -1,24 +0,0 @@
//===-- AArch64TargetObjectFile.cpp - AArch64 Object Info -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file deals with any AArch64 specific requirements on object files.
//
//===----------------------------------------------------------------------===//
#include "AArch64TargetObjectFile.h"
using namespace llvm;
void
AArch64ElfTargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
InitializeELF(TM.Options.UseInitArray);
}

31
lib/Target/AArch64/AArch64TargetObjectFile.h
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@ -1,31 +0,0 @@
//===-- AArch64TargetObjectFile.h - AArch64 Object Info ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file deals with any AArch64 specific requirements on object files.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64_TARGETOBJECTFILE_H
#define LLVM_TARGET_AARCH64_TARGETOBJECTFILE_H
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
/// AArch64ElfTargetObjectFile - This implementation is used for ELF
/// AArch64 targets.
class AArch64ElfTargetObjectFile : public TargetLoweringObjectFileELF {
void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
};
} // end namespace llvm
#endif

109
lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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@ -1,109 +0,0 @@
//===- AArch64TargetTransformInfo.cpp - AArch64 specific TTI pass ---------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// AArch64 target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/CostTable.h"
#include "llvm/Target/TargetLowering.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64tti"
// Declare the pass initialization routine locally as target-specific passes
// don't have a target-wide initialization entry point, and so we rely on the
// pass constructor initialization.
namespace llvm {
void initializeAArch64TTIPass(PassRegistry &);
}
namespace {
class AArch64TTI final : public ImmutablePass, public TargetTransformInfo {
const AArch64Subtarget *ST;
const AArch64TargetLowering *TLI;
public:
AArch64TTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
llvm_unreachable("This pass cannot be directly constructed");
}
AArch64TTI(const AArch64TargetMachine *TM)
: ImmutablePass(ID), ST(TM->getSubtargetImpl()),
TLI(TM->getTargetLowering()) {
initializeAArch64TTIPass(*PassRegistry::getPassRegistry());
}
virtual void initializePass() override {
pushTTIStack(this);
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
TargetTransformInfo::getAnalysisUsage(AU);
}
/// Pass identification.
static char ID;
/// Provide necessary pointer adjustments for the two base classes.
virtual void *getAdjustedAnalysisPointer(const void *ID) override {
if (ID == &TargetTransformInfo::ID)
return (TargetTransformInfo*)this;
return this;
}
/// \name Scalar TTI Implementations
/// @{
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector) const override {
if (Vector) {
if (ST->hasNEON())
return 32;
return 0;
}
return 32;
}
unsigned getRegisterBitWidth(bool Vector) const override {
if (Vector) {
if (ST->hasNEON())
return 128;
return 0;
}
return 64;
}
unsigned getMaximumUnrollFactor() const override { return 2; }
/// @}
};
} // end anonymous namespace
INITIALIZE_AG_PASS(AArch64TTI, TargetTransformInfo, "aarch64tti",
"AArch64 Target Transform Info", true, true, false)
char AArch64TTI::ID = 0;
ImmutablePass *
llvm::createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM) {
return new AArch64TTI(TM);
}

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lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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3
lib/Target/AArch64/AsmParser/CMakeLists.txt
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add_llvm_library(LLVMAArch64AsmParser
AArch64AsmParser.cpp
)

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lib/Target/AArch64/AsmParser/LLVMBuild.txt
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;===- ./lib/Target/AArch64/AsmParser/LLVMBuild.txt -------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = AArch64AsmParser
parent = AArch64
required_libraries = AArch64Desc AArch64Info AArch64Utils MC MCParser Support
add_to_library_groups = AArch64

15
lib/Target/AArch64/AsmParser/Makefile
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@ -1,15 +0,0 @@
##===- lib/Target/AArch64/AsmParser/Makefile ---------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAArch64AsmParser
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

37
lib/Target/AArch64/CMakeLists.txt
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set(LLVM_TARGET_DEFINITIONS AArch64.td)
tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(AArch64CommonTableGen)
add_llvm_target(AArch64CodeGen
AArch64AsmPrinter.cpp
AArch64BranchFixupPass.cpp
AArch64FrameLowering.cpp
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp
AArch64InstrInfo.cpp
AArch64MachineFunctionInfo.cpp
AArch64MCInstLower.cpp
AArch64RegisterInfo.cpp
AArch64SelectionDAGInfo.cpp
AArch64Subtarget.cpp
AArch64TargetMachine.cpp
AArch64TargetObjectFile.cpp
AArch64TargetTransformInfo.cpp
)
add_subdirectory(AsmParser)
add_subdirectory(Disassembler)
add_subdirectory(InstPrinter)
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
add_subdirectory(Utils)

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add_llvm_library(LLVMAArch64Disassembler
AArch64Disassembler.cpp
)

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lib/Target/AArch64/Disassembler/LLVMBuild.txt
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;===- ./lib/Target/AArch64/Disassembler/LLVMBuild.txt ----------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = AArch64Disassembler
parent = AArch64
required_libraries = AArch64Info AArch64Utils MC Support
add_to_library_groups = AArch64

16
lib/Target/AArch64/Disassembler/Makefile
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@ -1,16 +0,0 @@
##===- lib/Target/AArch64/Disassembler/Makefile ------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAArch64Disassembler
# Hack: we need to include 'main' target directory to grab private headers
CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

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lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
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//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an AArch64 MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include "AArch64InstPrinter.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "asm-printer"
#define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR
#include "AArch64GenAsmWriter.inc"
static int64_t unpackSignedImm(int BitWidth, uint64_t Value) {
assert(!(Value & ~((1ULL << BitWidth)-1)) && "immediate not n-bit");
if (Value & (1ULL << (BitWidth - 1)))
return static_cast<int64_t>(Value) - (1LL << BitWidth);
else
return Value;
}
AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
const MCInstrInfo &MII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI) :
MCInstPrinter(MAI, MII, MRI) {
// Initialize the set of available features.
setAvailableFeatures(STI.getFeatureBits());
}
void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << getRegisterName(RegNo);
}
void
AArch64InstPrinter::printOffsetSImm9Operand(const MCInst *MI,
unsigned OpNum, raw_ostream &O) {
const MCOperand &MOImm = MI->getOperand(OpNum);
int32_t Imm = unpackSignedImm(9, MOImm.getImm());
O << '#' << Imm;
}
void
AArch64InstPrinter::printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, unsigned MemSize,
unsigned RmSize) {
unsigned ExtImm = MI->getOperand(OpNum).getImm();
unsigned OptionHi = ExtImm >> 1;
unsigned S = ExtImm & 1;
bool IsLSL = OptionHi == 1 && RmSize == 64;
const char *Ext;
switch (OptionHi) {
case 1:
Ext = (RmSize == 32) ? "uxtw" : "lsl";
break;
case 3:
Ext = (RmSize == 32) ? "sxtw" : "sxtx";
break;
default:
llvm_unreachable("Incorrect Option on load/store (reg offset)");
}
O << Ext;
if (S) {
unsigned ShiftAmt = Log2_32(MemSize);
O << " #" << ShiftAmt;
} else if (IsLSL) {
O << " #0";
}
}
void
AArch64InstPrinter::printAddSubImmLSL0Operand(const MCInst *MI,
unsigned OpNum, raw_ostream &O) {
const MCOperand &Imm12Op = MI->getOperand(OpNum);
if (Imm12Op.isImm()) {
int64_t Imm12 = Imm12Op.getImm();
assert(Imm12 >= 0 && "Invalid immediate for add/sub imm");
O << "#" << Imm12;
} else {
assert(Imm12Op.isExpr() && "Unexpected shift operand type");
O << "#" << *Imm12Op.getExpr();
}
}
void
AArch64InstPrinter::printAddSubImmLSL12Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
printAddSubImmLSL0Operand(MI, OpNum, O);
O << ", lsl #12";
}
void
AArch64InstPrinter::printBareImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
O << MO.getImm();
}
template<unsigned RegWidth> void
AArch64InstPrinter::printBFILSBOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &ImmROp = MI->getOperand(OpNum);
unsigned LSB = ImmROp.getImm() == 0 ? 0 : RegWidth - ImmROp.getImm();
O << '#' << LSB;
}
void AArch64InstPrinter::printBFIWidthOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &ImmSOp = MI->getOperand(OpNum);
unsigned Width = ImmSOp.getImm() + 1;
O << '#' << Width;
}
void
AArch64InstPrinter::printBFXWidthOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &ImmSOp = MI->getOperand(OpNum);
const MCOperand &ImmROp = MI->getOperand(OpNum - 1);
unsigned ImmR = ImmROp.getImm();
unsigned ImmS = ImmSOp.getImm();
assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract");
O << '#' << (ImmS - ImmR + 1);
}
void
AArch64InstPrinter::printCRxOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &CRx = MI->getOperand(OpNum);
O << 'c' << CRx.getImm();
}
void
AArch64InstPrinter::printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &ScaleOp = MI->getOperand(OpNum);
O << '#' << (64 - ScaleOp.getImm());
}
void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &o) {
const MCOperand &MOImm8 = MI->getOperand(OpNum);
assert(MOImm8.isImm()
&& "Immediate operand required for floating-point immediate inst");
uint32_t Imm8 = MOImm8.getImm();
uint32_t Fraction = Imm8 & 0xf;
uint32_t Exponent = (Imm8 >> 4) & 0x7;
uint32_t Negative = (Imm8 >> 7) & 0x1;
float Val = 1.0f + Fraction / 16.0f;
// That is:
// 000 -> 2^1, 001 -> 2^2, 010 -> 2^3, 011 -> 2^4,
// 100 -> 2^-3, 101 -> 2^-2, 110 -> 2^-1, 111 -> 2^0
if (Exponent & 0x4) {
Val /= 1 << (7 - Exponent);
} else {
Val *= 1 << (Exponent + 1);
}
Val = Negative ? -Val : Val;
o << '#' << format("%.8f", Val);
}
void AArch64InstPrinter::printFPZeroOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &o) {
o << "#0.0";
}
void
AArch64InstPrinter::printCondCodeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
O << A64CondCodeToString(static_cast<A64CC::CondCodes>(MO.getImm()));
}
void
AArch64InstPrinter::printInverseCondCodeOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
A64CC::CondCodes CC =
static_cast<A64CC::CondCodes>(MI->getOperand(OpNum).getImm());
O << A64CondCodeToString(A64InvertCondCode(CC));
}
template <unsigned field_width, unsigned scale> void
AArch64InstPrinter::printLabelOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
if (!MO.isImm()) {
printOperand(MI, OpNum, O);
return;
}
// The immediate of LDR (lit) instructions is a signed 19-bit immediate, which
// is multiplied by 4 (because all A64 instructions are 32-bits wide).
uint64_t UImm = MO.getImm();
uint64_t Sign = UImm & (1LL << (field_width - 1));
int64_t SImm = scale * ((UImm & ~Sign) - Sign);
O << "#" << SImm;
}
template<unsigned RegWidth> void
AArch64InstPrinter::printLogicalImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
uint64_t Val;
A64Imms::isLogicalImmBits(RegWidth, MO.getImm(), Val);
O << "#0x";
O.write_hex(Val);
}
void
AArch64InstPrinter::printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, int MemSize) {
const MCOperand &MOImm = MI->getOperand(OpNum);
if (MOImm.isImm()) {
uint32_t Imm = MOImm.getImm() * MemSize;
O << "#" << Imm;
} else {
O << "#" << *MOImm.getExpr();
}
}
void
AArch64InstPrinter::printShiftOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O,
A64SE::ShiftExtSpecifiers Shift) {
const MCOperand &MO = MI->getOperand(OpNum);
// LSL #0 is not printed
if (Shift == A64SE::LSL && MO.isImm() && MO.getImm() == 0)
return;
switch (Shift) {
case A64SE::LSL: O << "lsl"; break;
case A64SE::LSR: O << "lsr"; break;
case A64SE::ASR: O << "asr"; break;
case A64SE::ROR: O << "ror"; break;
default: llvm_unreachable("Invalid shift specifier in logical instruction");
}
O << " #" << MO.getImm();
}
void
AArch64InstPrinter::printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &UImm16MO = MI->getOperand(OpNum);
const MCOperand &ShiftMO = MI->getOperand(OpNum + 1);
if (UImm16MO.isImm()) {
O << '#' << UImm16MO.getImm();
if (ShiftMO.getImm() != 0)
O << ", lsl #" << (ShiftMO.getImm() * 16);
return;
}
O << "#" << *UImm16MO.getExpr();
}
void AArch64InstPrinter::printNamedImmOperand(const NamedImmMapper &Mapper,
const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
bool ValidName;
const MCOperand &MO = MI->getOperand(OpNum);
StringRef Name = Mapper.toString(MO.getImm(), ValidName);
if (ValidName)
O << Name;
else
O << '#' << MO.getImm();
}
void
AArch64InstPrinter::printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
bool ValidName;
std::string Name = Mapper.toString(MO.getImm(), ValidName);
if (ValidName) {
O << Name;
return;
}
}
void AArch64InstPrinter::printRegExtendOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O,
A64SE::ShiftExtSpecifiers Ext) {
// FIXME: In principle TableGen should be able to detect this itself far more
// easily. We will only accumulate more of these hacks.
unsigned Reg0 = MI->getOperand(0).getReg();
unsigned Reg1 = MI->getOperand(1).getReg();
if (isStackReg(Reg0) || isStackReg(Reg1)) {
A64SE::ShiftExtSpecifiers LSLEquiv;
if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
LSLEquiv = A64SE::UXTX;
else
LSLEquiv = A64SE::UXTW;
if (Ext == LSLEquiv) {
O << "lsl #" << MI->getOperand(OpNum).getImm();
return;
}
}
switch (Ext) {
case A64SE::UXTB: O << "uxtb"; break;
case A64SE::UXTH: O << "uxth"; break;
case A64SE::UXTW: O << "uxtw"; break;
case A64SE::UXTX: O << "uxtx"; break;
case A64SE::SXTB: O << "sxtb"; break;
case A64SE::SXTH: O << "sxth"; break;
case A64SE::SXTW: O << "sxtw"; break;
case A64SE::SXTX: O << "sxtx"; break;
default: llvm_unreachable("Unexpected shift type for printing");
}
const MCOperand &MO = MI->getOperand(OpNum);
if (MO.getImm() != 0)
O << " #" << MO.getImm();
}
template<int MemScale> void
AArch64InstPrinter::printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MOImm = MI->getOperand(OpNum);
int32_t Imm = unpackSignedImm(7, MOImm.getImm());
O << "#" << (Imm * MemScale);
}
void AArch64InstPrinter::printVPRRegister(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNo).getReg();
std::string Name = getRegisterName(Reg);
Name[0] = 'v';
O << Name;
}
void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
unsigned Reg = Op.getReg();
O << getRegisterName(Reg);
} else if (Op.isImm()) {
O << '#' << Op.getImm();
} else {
assert(Op.isExpr() && "unknown operand kind in printOperand");
// If a symbolic branch target was added as a constant expression then print
// that address in hex.
const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
int64_t Address;
if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
O << "0x";
O.write_hex(Address);
}
else {
// Otherwise, just print the expression.
O << *Op.getExpr();
}
}
}
void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot) {
if (MI->getOpcode() == AArch64::TLSDESCCALL) {
// This is a special assembler directive which applies an
// R_AARCH64_TLSDESC_CALL to the following (BLR) instruction. It has a fixed
// form outside the normal TableGenerated scheme.
O << "\t.tlsdesccall " << *MI->getOperand(0).getExpr();
} else if (!printAliasInstr(MI, O))
printInstruction(MI, O);
printAnnotation(O, Annot);
}
template <A64SE::ShiftExtSpecifiers Ext, bool isHalf>
void AArch64InstPrinter::printNeonMovImmShiftOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
assert(MO.isImm() &&
"Immediate operand required for Neon vector immediate inst.");
bool IsLSL = false;
if (Ext == A64SE::LSL)
IsLSL = true;
else if (Ext != A64SE::MSL)
llvm_unreachable("Invalid shift specifier in movi instruction");
int64_t Imm = MO.getImm();
// MSL and LSLH accepts encoded shift amount 0 or 1.
if ((!IsLSL || (IsLSL && isHalf)) && Imm != 0 && Imm != 1)
llvm_unreachable("Invalid shift amount in movi instruction");
// LSH accepts encoded shift amount 0, 1, 2 or 3.
if (IsLSL && (Imm < 0 || Imm > 3))
llvm_unreachable("Invalid shift amount in movi instruction");
// Print shift amount as multiple of 8 with MSL encoded shift amount
// 0 and 1 printed as 8 and 16.
if (!IsLSL)
Imm++;
Imm *= 8;
// LSL #0 is not printed
if (IsLSL) {
if (Imm == 0)
return;
O << ", lsl";
} else
O << ", msl";
O << " #" << Imm;
}
void AArch64InstPrinter::printNeonUImm0Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &o) {
o << "#0x0";
}
void AArch64InstPrinter::printUImmHexOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MOUImm = MI->getOperand(OpNum);
assert(MOUImm.isImm() &&
"Immediate operand required for Neon vector immediate inst.");
unsigned Imm = MOUImm.getImm();
O << "#0x";
O.write_hex(Imm);
}
void AArch64InstPrinter::printUImmBareOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
const MCOperand &MOUImm = MI->getOperand(OpNum);
assert(MOUImm.isImm()
&& "Immediate operand required for Neon vector immediate inst.");
unsigned Imm = MOUImm.getImm();
O << Imm;
}
void AArch64InstPrinter::printNeonUImm64MaskOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
const MCOperand &MOUImm8 = MI->getOperand(OpNum);
assert(MOUImm8.isImm() &&
"Immediate operand required for Neon vector immediate bytemask inst.");
uint32_t UImm8 = MOUImm8.getImm();
uint64_t Mask = 0;
// Replicates 0x00 or 0xff byte in a 64-bit vector
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
if ((UImm8 >> ByteNum) & 1)
Mask |= (uint64_t)0xff << (8 * ByteNum);
}
O << "#0x";
O.write_hex(Mask);
}
// If Count > 1, there are two valid kinds of vector list:
// (1) {Vn.layout, Vn+1.layout, ... , Vm.layout}
// (2) {Vn.layout - Vm.layout}
// We choose the first kind as output.
template <A64Layout::VectorLayout Layout, unsigned Count>
void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
assert(Count >= 1 && Count <= 4 && "Invalid Number of Vectors");
unsigned Reg = MI->getOperand(OpNum).getReg();
std::string LayoutStr = A64VectorLayoutToString(Layout);
O << "{ ";
if (Count > 1) { // Print sub registers separately
bool IsVec64 = (Layout < A64Layout::VL_16B);
unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0;
for (unsigned I = 0; I < Count; I++) {
std::string Name = getRegisterName(MRI.getSubReg(Reg, SubRegIdx++));
Name[0] = 'v';
O << Name << LayoutStr;
if (I != Count - 1)
O << ", ";
}
} else { // Print the register directly when NumVecs is 1.
std::string Name = getRegisterName(Reg);
Name[0] = 'v';
O << Name << LayoutStr;
}
O << " }";
}

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lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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@ -1,186 +0,0 @@
//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an AArch64 MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64INSTPRINTER_H
#define LLVM_AARCH64INSTPRINTER_H
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCSubtargetInfo.h"
namespace llvm {
class MCOperand;
class AArch64InstPrinter : public MCInstPrinter {
public:
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
// Autogenerated by tblgen
void printInstruction(const MCInst *MI, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
static const char *getInstructionName(unsigned Opcode);
void printRegName(raw_ostream &O, unsigned RegNum) const override;
template<unsigned MemSize, unsigned RmSize>
void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize);
}
void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, unsigned MemSize,
unsigned RmSize);
void printAddSubImmLSL0Operand(const MCInst *MI,
unsigned OpNum, raw_ostream &O);
void printAddSubImmLSL12Operand(const MCInst *MI,
unsigned OpNum, raw_ostream &O);
void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
template<unsigned RegWidth>
void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printBFXWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printInverseCondCodeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printCRxOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
void printFPZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
template<int MemScale>
void printOffsetUImm12Operand(const MCInst *MI,
unsigned OpNum, raw_ostream &o) {
printOffsetUImm12Operand(MI, OpNum, o, MemScale);
}
void printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &o, int MemScale);
template<unsigned field_width, unsigned scale>
void printLabelOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
template<unsigned RegWidth>
void printLogicalImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
template<typename SomeNamedImmMapper>
void printNamedImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
printNamedImmOperand(SomeNamedImmMapper(), MI, OpNum, O);
}
void printNamedImmOperand(const NamedImmMapper &Mapper,
const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printMRSOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
printSysRegOperand(A64SysReg::MRSMapper(), MI, OpNum, O);
}
void printMSROperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
printSysRegOperand(A64SysReg::MSRMapper(), MI, OpNum, O);
}
void printShiftOperand(const char *name, const MCInst *MI,
unsigned OpIdx, raw_ostream &O);
void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printLSROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printShiftOperand("lsr", MI, OpNum, O);
}
void printASROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printShiftOperand("asr", MI, OpNum, O);
}
void printROROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printShiftOperand("ror", MI, OpNum, O);
}
template<A64SE::ShiftExtSpecifiers Shift>
void printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printShiftOperand(MI, OpNum, O, Shift);
}
void printShiftOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, A64SE::ShiftExtSpecifiers Sh);
void printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
template<int MemSize> void
printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printOffsetSImm9Operand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printPRFMOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
template<A64SE::ShiftExtSpecifiers EXT>
void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
printRegExtendOperand(MI, OpNum, O, EXT);
}
void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O, A64SE::ShiftExtSpecifiers Ext);
void printVPRRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
bool isStackReg(unsigned RegNo) {
return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
}
template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
void printNeonMovImmShiftOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printNeonUImm0Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printUImmHexOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printUImmBareOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printNeonUImm64MaskOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
template <A64Layout::VectorLayout Layout, unsigned Count>
void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
};
}
#endif

3
lib/Target/AArch64/InstPrinter/CMakeLists.txt
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@ -1,3 +0,0 @@
add_llvm_library(LLVMAArch64AsmPrinter
AArch64InstPrinter.cpp
)

24
lib/Target/AArch64/InstPrinter/LLVMBuild.txt
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@ -1,24 +0,0 @@
;===- ./lib/Target/AArch64/InstPrinter/LLVMBuild.txt -----------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = AArch64AsmPrinter
parent = AArch64
required_libraries = AArch64Utils MC Support
add_to_library_groups = AArch64

15
lib/Target/AArch64/InstPrinter/Makefile
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@ -1,15 +0,0 @@
##===- lib/Target/AArch64/AsmPrinter/Makefile --------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAArch64AsmPrinter
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

35
lib/Target/AArch64/LLVMBuild.txt
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@ -1,35 +0,0 @@
;===- ./lib/Target/AArch64/LLVMBuild.txt -----------------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[common]
subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
[component_0]
type = TargetGroup
name = AArch64
parent = Target
has_asmparser = 1
has_asmprinter = 1
has_disassembler = 1
has_jit = 1
[component_1]
type = Library
name = AArch64CodeGen
parent = AArch64
required_libraries = AArch64AsmPrinter AArch64Desc AArch64Info AArch64Utils Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target
add_to_library_groups = AArch64

593
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
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//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the AArch64 implementation of the MCAsmBackend class,
// which is principally concerned with relaxation of the various fixup kinds.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AArch64FixupKinds.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
class AArch64AsmBackend : public MCAsmBackend {
const MCSubtargetInfo* STI;
public:
AArch64AsmBackend(const Target &T, const StringRef TT)
: MCAsmBackend(),
STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", ""))
{}
~AArch64AsmBackend() {
delete STI;
}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
virtual void processFixupValue(const MCAssembler &Asm,
const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF,
const MCValue &Target, uint64_t &Value,
bool &IsResolved) override;
};
} // end anonymous namespace
void AArch64AsmBackend::processFixupValue(const MCAssembler &Asm,
const MCAsmLayout &Layout,
const MCFixup &Fixup,
const MCFragment *DF,
const MCValue &Target,
uint64_t &Value, bool &IsResolved) {
// The ADRP instruction adds some multiple of 0x1000 to the current PC &
// ~0xfff. This means that the required offset to reach a symbol can vary by
// up to one step depending on where the ADRP is in memory. For example:
//
// ADRP x0, there
// there:
//
// If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
// we'll need that as an offset. At any other address "there" will be in the
// same page as the ADRP and the instruction should encode 0x0. Assuming the
// section isn't 0x1000-aligned, we therefore need to delegate this decision
// to the linker -- a relocation!
if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_page ||
(uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_got_page ||
(uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_gottprel_page ||
(uint32_t)Fixup.getKind() == AArch64::fixup_a64_tlsdesc_adr_page)
IsResolved = false;
}
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value);
namespace {
class ELFAArch64AsmBackend : public AArch64AsmBackend {
uint8_t OSABI;
bool IsLittle; // Big or little endian
public:
ELFAArch64AsmBackend(const Target &T, const StringRef TT,
uint8_t _OSABI, bool isLittle)
: AArch64AsmBackend(T, TT), OSABI(_OSABI), IsLittle(isLittle) { }
bool fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const override;
unsigned int getNumFixupKinds() const override {
return AArch64::NumTargetFixupKinds;
}
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
// This table *must* be in the order that the fixup_* kinds are defined in
// AArch64FixupKinds.h.
//
// Name Offset (bits) Size (bits) Flags
{ "fixup_a64_ld_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_adr_prel", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_adr_prel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_add_lo12", 0, 32, 0 },
{ "fixup_a64_ldst8_lo12", 0, 32, 0 },
{ "fixup_a64_ldst16_lo12", 0, 32, 0 },
{ "fixup_a64_ldst32_lo12", 0, 32, 0 },
{ "fixup_a64_ldst64_lo12", 0, 32, 0 },
{ "fixup_a64_ldst128_lo12", 0, 32, 0 },
{ "fixup_a64_tstbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_condbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_uncondbr", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_call", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_movw_uabs_g0", 0, 32, 0 },
{ "fixup_a64_movw_uabs_g0_nc", 0, 32, 0 },
{ "fixup_a64_movw_uabs_g1", 0, 32, 0 },
{ "fixup_a64_movw_uabs_g1_nc", 0, 32, 0 },
{ "fixup_a64_movw_uabs_g2", 0, 32, 0 },
{ "fixup_a64_movw_uabs_g2_nc", 0, 32, 0 },
{ "fixup_a64_movw_uabs_g3", 0, 32, 0 },
{ "fixup_a64_movw_sabs_g0", 0, 32, 0 },
{ "fixup_a64_movw_sabs_g1", 0, 32, 0 },
{ "fixup_a64_movw_sabs_g2", 0, 32, 0 },
{ "fixup_a64_adr_prel_got_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_ld64_got_lo12_nc", 0, 32, 0 },
{ "fixup_a64_movw_dtprel_g2", 0, 32, 0 },
{ "fixup_a64_movw_dtprel_g1", 0, 32, 0 },
{ "fixup_a64_movw_dtprel_g1_nc", 0, 32, 0 },
{ "fixup_a64_movw_dtprel_g0", 0, 32, 0 },
{ "fixup_a64_movw_dtprel_g0_nc", 0, 32, 0 },
{ "fixup_a64_add_dtprel_hi12", 0, 32, 0 },
{ "fixup_a64_add_dtprel_lo12", 0, 32, 0 },
{ "fixup_a64_add_dtprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst8_dtprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst8_dtprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst16_dtprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst16_dtprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst32_dtprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst32_dtprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst64_dtprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst64_dtprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_movw_gottprel_g1", 0, 32, 0 },
{ "fixup_a64_movw_gottprel_g0_nc", 0, 32, 0 },
{ "fixup_a64_adr_gottprel_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_ld64_gottprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ld_gottprel_prel19", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_movw_tprel_g2", 0, 32, 0 },
{ "fixup_a64_movw_tprel_g1", 0, 32, 0 },
{ "fixup_a64_movw_tprel_g1_nc", 0, 32, 0 },
{ "fixup_a64_movw_tprel_g0", 0, 32, 0 },
{ "fixup_a64_movw_tprel_g0_nc", 0, 32, 0 },
{ "fixup_a64_add_tprel_hi12", 0, 32, 0 },
{ "fixup_a64_add_tprel_lo12", 0, 32, 0 },
{ "fixup_a64_add_tprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst8_tprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst8_tprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst16_tprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst16_tprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst32_tprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst32_tprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_ldst64_tprel_lo12", 0, 32, 0 },
{ "fixup_a64_ldst64_tprel_lo12_nc", 0, 32, 0 },
{ "fixup_a64_tlsdesc_adr_page", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_a64_tlsdesc_ld64_lo12_nc", 0, 32, 0 },
{ "fixup_a64_tlsdesc_add_lo12_nc", 0, 32, 0 },
{ "fixup_a64_tlsdesc_call", 0, 0, 0 }
};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
}
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value, bool IsPCRel) const override {
unsigned NumBytes = getFixupKindInfo(Fixup.getKind()).TargetSize / 8;
Value = adjustFixupValue(Fixup.getKind(), Value);
if (!Value) return; // Doesn't change encoding.
unsigned Offset = Fixup.getOffset();
assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
// For each byte of the fragment that the fixup touches, mask in the bits
// from the fixup value.
for (unsigned i = 0; i != NumBytes; ++i) {
Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
}
}
bool mayNeedRelaxation(const MCInst&) const override {
return false;
}
void relaxInstruction(const MCInst&, llvm::MCInst&) const override {
llvm_unreachable("Cannot relax instructions");
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
return createAArch64ELFObjectWriter(OS, OSABI, IsLittle);
}
};
} // end anonymous namespace
bool
ELFAArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const {
// Correct for now. With all instructions 32-bit only very low-level
// considerations could make you select something which may fail.
return false;
}
bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
// Can't emit NOP with size not multiple of 32-bits
if (Count % 4 != 0)
return false;
uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
OW->Write32(0xd503201f);
return true;
}
static unsigned ADRImmBits(unsigned Value) {
unsigned lo2 = Value & 0x3;
unsigned hi19 = (Value & 0x1fffff) >> 2;
return (hi19 << 5) | (lo2 << 29);
}
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
switch (Kind) {
default:
llvm_unreachable("Unknown fixup kind!");
case FK_Data_2:
assert((int64_t)Value >= -32768 &&
(int64_t)Value <= 65536 &&
"Out of range ABS16 fixup");
return Value;
case FK_Data_4:
assert((int64_t)Value >= -(1LL << 31) &&
(int64_t)Value <= (1LL << 32) - 1 &&
"Out of range ABS32 fixup");
return Value;
case FK_Data_8:
return Value;
case AArch64::fixup_a64_ld_gottprel_prel19:
// R_AARCH64_LD_GOTTPREL_PREL19: Set a load-literal immediate to bits 1F
// FFFC of G(TPREL(S+A)) - P; check -2^20 <= X < 2^20.
case AArch64::fixup_a64_ld_prel:
// R_AARCH64_LD_PREL_LO19: Sets a load-literal (immediate) value to bits
// 1F FFFC of S+A-P, checking that -2^20 <= S+A-P < 2^20.
assert((int64_t)Value >= -(1LL << 20) &&
(int64_t)Value < (1LL << 20) && "Out of range LDR (lit) fixup");
return (Value & 0x1ffffc) << 3;
case AArch64::fixup_a64_adr_prel:
// R_AARCH64_ADR_PREL_LO21: Sets an ADR immediate value to bits 1F FFFF of
// the result of S+A-P, checking that -2^20 <= S+A-P < 2^20.
assert((int64_t)Value >= -(1LL << 20) &&
(int64_t)Value < (1LL << 20) && "Out of range ADR fixup");
return ADRImmBits(Value & 0x1fffff);
case AArch64::fixup_a64_adr_prel_page:
// R_AARCH64_ADR_PREL_PG_HI21: Sets an ADRP immediate value to bits 1 FFFF
// F000 of the result of the operation, checking that -2^32 <= result <
// 2^32.
assert((int64_t)Value >= -(1LL << 32) &&
(int64_t)Value < (1LL << 32) && "Out of range ADRP fixup");
return ADRImmBits((Value & 0x1fffff000ULL) >> 12);
case AArch64::fixup_a64_add_dtprel_hi12:
// R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits
// FF F000 of DTPREL(S+A), check 0 <= X < 2^24.
case AArch64::fixup_a64_add_tprel_hi12:
// R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits
// FF F000 of TPREL(S+A), check 0 <= X < 2^24.
assert((int64_t)Value >= 0 &&
(int64_t)Value < (1LL << 24) && "Out of range ADD fixup");
return (Value & 0xfff000) >> 2;
case AArch64::fixup_a64_add_dtprel_lo12:
// R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits
// FFF of DTPREL(S+A), check 0 <= X < 2^12.
case AArch64::fixup_a64_add_tprel_lo12:
// R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits
// FFF of TPREL(S+A), check 0 <= X < 2^12.
assert((int64_t)Value >= 0 &&
(int64_t)Value < (1LL << 12) && "Out of range ADD fixup");
// ... fallthrough to no-checking versions ...
case AArch64::fixup_a64_add_dtprel_lo12_nc:
// R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: Set an ADD immediate field to bits
// FFF of DTPREL(S+A) with no overflow check.
case AArch64::fixup_a64_add_tprel_lo12_nc:
// R_AARCH64_TLSLD_ADD_TPREL_LO12_NC: Set an ADD immediate field to bits
// FFF of TPREL(S+A) with no overflow check.
case AArch64::fixup_a64_tlsdesc_add_lo12_nc:
// R_AARCH64_TLSDESC_ADD_LO12_NC: Set an ADD immediate field to bits
// FFF of G(TLSDESC(S+A)), with no overflow check.
case AArch64::fixup_a64_add_lo12:
// R_AARCH64_ADD_ABS_LO12_NC: Sets an ADD immediate value to bits FFF of
// S+A, with no overflow check.
return (Value & 0xfff) << 10;
case AArch64::fixup_a64_ldst8_dtprel_lo12:
// R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF
// of DTPREL(S+A), check 0 <= X < 2^12.
case AArch64::fixup_a64_ldst8_tprel_lo12:
// R_AARCH64_TLSLE_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF
// of DTPREL(S+A), check 0 <= X < 2^12.
assert((int64_t) Value >= 0 &&
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
// ... fallthrough to no-checking versions ...
case AArch64::fixup_a64_ldst8_dtprel_lo12_nc:
// R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF
// of DTPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst8_tprel_lo12_nc:
// R_AARCH64_TLSLD_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF
// of TPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst8_lo12:
// R_AARCH64_LDST8_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFF
// of S+A, with no overflow check.
return (Value & 0xfff) << 10;
case AArch64::fixup_a64_ldst16_dtprel_lo12:
// R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE
// of DTPREL(S+A), check 0 <= X < 2^12.
case AArch64::fixup_a64_ldst16_tprel_lo12:
// R_AARCH64_TLSLE_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE
// of DTPREL(S+A), check 0 <= X < 2^12.
assert((int64_t) Value >= 0 &&
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
// ... fallthrough to no-checking versions ...
case AArch64::fixup_a64_ldst16_dtprel_lo12_nc:
// R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE
// of DTPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst16_tprel_lo12_nc:
// R_AARCH64_TLSLD_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE
// of TPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst16_lo12:
// R_AARCH64_LDST16_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFE
// of S+A, with no overflow check.
return (Value & 0xffe) << 9;
case AArch64::fixup_a64_ldst32_dtprel_lo12:
// R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC
// of DTPREL(S+A), check 0 <= X < 2^12.
case AArch64::fixup_a64_ldst32_tprel_lo12:
// R_AARCH64_TLSLE_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC
// of DTPREL(S+A), check 0 <= X < 2^12.
assert((int64_t) Value >= 0 &&
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
// ... fallthrough to no-checking versions ...
case AArch64::fixup_a64_ldst32_dtprel_lo12_nc:
// R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC
// of DTPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst32_tprel_lo12_nc:
// R_AARCH64_TLSLD_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC
// of TPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst32_lo12:
// R_AARCH64_LDST32_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFC
// of S+A, with no overflow check.
return (Value & 0xffc) << 8;
case AArch64::fixup_a64_ldst64_dtprel_lo12:
// R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8
// of DTPREL(S+A), check 0 <= X < 2^12.
case AArch64::fixup_a64_ldst64_tprel_lo12:
// R_AARCH64_TLSLE_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8
// of DTPREL(S+A), check 0 <= X < 2^12.
assert((int64_t) Value >= 0 &&
(int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
// ... fallthrough to no-checking versions ...
case AArch64::fixup_a64_ldst64_dtprel_lo12_nc:
// R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8
// of DTPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst64_tprel_lo12_nc:
// R_AARCH64_TLSLD_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8
// of TPREL(S+A), with no overflow check.
case AArch64::fixup_a64_ldst64_lo12:
// R_AARCH64_LDST64_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF8
// of S+A, with no overflow check.
return (Value & 0xff8) << 7;
case AArch64::fixup_a64_ldst128_lo12:
// R_AARCH64_LDST128_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF0
// of S+A, with no overflow check.
return (Value & 0xff0) << 6;
case AArch64::fixup_a64_movw_uabs_g0:
// R_AARCH64_MOVW_UABS_G0: Sets a MOVZ immediate field to bits FFFF of S+A
// with a check that S+A < 2^16
assert(Value <= 0xffff && "Out of range move wide fixup");
return (Value & 0xffff) << 5;
case AArch64::fixup_a64_movw_dtprel_g0_nc:
// R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: Sets a MOVK immediate field to bits
// FFFF of DTPREL(S+A) with no overflow check.
case AArch64::fixup_a64_movw_gottprel_g0_nc:
// R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: Sets a MOVK immediate field to bits
// FFFF of G(TPREL(S+A)) - GOT with no overflow check.
case AArch64::fixup_a64_movw_tprel_g0_nc:
// R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: Sets a MOVK immediate field to bits
// FFFF of TPREL(S+A) with no overflow check.
case AArch64::fixup_a64_movw_uabs_g0_nc:
// R_AARCH64_MOVW_UABS_G0_NC: Sets a MOVK immediate field to bits FFFF of
// S+A with no overflow check.
return (Value & 0xffff) << 5;
case AArch64::fixup_a64_movw_uabs_g1:
// R_AARCH64_MOVW_UABS_G1: Sets a MOVZ immediate field to bits FFFF0000 of
// S+A with a check that S+A < 2^32
assert(Value <= 0xffffffffull && "Out of range move wide fixup");
return ((Value >> 16) & 0xffff) << 5;
case AArch64::fixup_a64_movw_dtprel_g1_nc:
// R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: Set a MOVK immediate field
// to bits FFFF0000 of DTPREL(S+A), with no overflow check.
case AArch64::fixup_a64_movw_tprel_g1_nc:
// R_AARCH64_TLSLD_MOVW_TPREL_G1_NC: Set a MOVK immediate field
// to bits FFFF0000 of TPREL(S+A), with no overflow check.
case AArch64::fixup_a64_movw_uabs_g1_nc:
// R_AARCH64_MOVW_UABS_G1_NC: Sets a MOVK immediate field to bits
// FFFF0000 of S+A with no overflow check.
return ((Value >> 16) & 0xffff) << 5;
case AArch64::fixup_a64_movw_uabs_g2:
// R_AARCH64_MOVW_UABS_G2: Sets a MOVZ immediate field to bits FFFF 0000
// 0000 of S+A with a check that S+A < 2^48
assert(Value <= 0xffffffffffffull && "Out of range move wide fixup");
return ((Value >> 32) & 0xffff) << 5;
case AArch64::fixup_a64_movw_uabs_g2_nc:
// R_AARCH64_MOVW_UABS_G2: Sets a MOVK immediate field to bits FFFF 0000
// 0000 of S+A with no overflow check.
return ((Value >> 32) & 0xffff) << 5;
case AArch64::fixup_a64_movw_uabs_g3:
// R_AARCH64_MOVW_UABS_G3: Sets a MOVZ immediate field to bits FFFF 0000
// 0000 0000 of S+A (no overflow check needed)
return ((Value >> 48) & 0xffff) << 5;
case AArch64::fixup_a64_movw_dtprel_g0:
// R_AARCH64_TLSLD_MOVW_DTPREL_G0: Set a MOV[NZ] immediate field
// to bits FFFF of DTPREL(S+A).
case AArch64::fixup_a64_movw_tprel_g0:
// R_AARCH64_TLSLE_MOVW_TPREL_G0: Set a MOV[NZ] immediate field to
// bits FFFF of TPREL(S+A).
case AArch64::fixup_a64_movw_sabs_g0: {
// R_AARCH64_MOVW_SABS_G0: Sets MOV[NZ] immediate field using bits FFFF of
// S+A (see notes below); check -2^16 <= S+A < 2^16. (notes say that we
// should convert between MOVN and MOVZ to achieve our goals).
int64_t Signed = Value;
assert(Signed >= -(1LL << 16) && Signed < (1LL << 16)
&& "Out of range move wide fixup");
if (Signed >= 0) {
Value = (Value & 0xffff) << 5;
// Bit 30 converts the MOVN encoding into a MOVZ
Value |= 1 << 30;
} else {
// MCCodeEmitter should have encoded a MOVN, which is fine.
Value = (~Value & 0xffff) << 5;
}
return Value;
}
case AArch64::fixup_a64_movw_dtprel_g1:
// R_AARCH64_TLSLD_MOVW_DTPREL_G1: Set a MOV[NZ] immediate field
// to bits FFFF0000 of DTPREL(S+A).
case AArch64::fixup_a64_movw_gottprel_g1:
// R_AARCH64_TLSIE_MOVW_GOTTPREL_G1: Set a MOV[NZ] immediate field
// to bits FFFF0000 of G(TPREL(S+A)) - GOT.
case AArch64::fixup_a64_movw_tprel_g1:
// R_AARCH64_TLSLE_MOVW_TPREL_G1: Set a MOV[NZ] immediate field to
// bits FFFF0000 of TPREL(S+A).
case AArch64::fixup_a64_movw_sabs_g1: {
// R_AARCH64_MOVW_SABS_G1: Sets MOV[NZ] immediate field using bits FFFF 0000
// of S+A (see notes below); check -2^32 <= S+A < 2^32. (notes say that we
// should convert between MOVN and MOVZ to achieve our goals).
int64_t Signed = Value;
assert(Signed >= -(1LL << 32) && Signed < (1LL << 32)
&& "Out of range move wide fixup");
if (Signed >= 0) {
Value = ((Value >> 16) & 0xffff) << 5;
// Bit 30 converts the MOVN encoding into a MOVZ
Value |= 1 << 30;
} else {
Value = ((~Value >> 16) & 0xffff) << 5;
}
return Value;
}
case AArch64::fixup_a64_movw_dtprel_g2:
// R_AARCH64_TLSLD_MOVW_DTPREL_G2: Set a MOV[NZ] immediate field
// to bits FFFF 0000 0000 of DTPREL(S+A).
case AArch64::fixup_a64_movw_tprel_g2:
// R_AARCH64_TLSLE_MOVW_TPREL_G2: Set a MOV[NZ] immediate field to
// bits FFFF 0000 0000 of TPREL(S+A).
case AArch64::fixup_a64_movw_sabs_g2: {
// R_AARCH64_MOVW_SABS_G2: Sets MOV[NZ] immediate field using bits FFFF 0000
// 0000 of S+A (see notes below); check -2^48 <= S+A < 2^48. (notes say that
// we should convert between MOVN and MOVZ to achieve our goals).
int64_t Signed = Value;
assert(Signed >= -(1LL << 48) && Signed < (1LL << 48)
&& "Out of range move wide fixup");
if (Signed >= 0) {
Value = ((Value >> 32) & 0xffff) << 5;
// Bit 30 converts the MOVN encoding into a MOVZ
Value |= 1 << 30;
} else {
Value = ((~Value >> 32) & 0xffff) << 5;
}
return Value;
}
case AArch64::fixup_a64_tstbr:
// R_AARCH64_TSTBR14: Sets the immediate field of a TBZ/TBNZ instruction to
// bits FFFC of S+A-P, checking -2^15 <= S+A-P < 2^15.
assert((int64_t)Value >= -(1LL << 15) &&
(int64_t)Value < (1LL << 15) && "Out of range TBZ/TBNZ fixup");
return (Value & 0xfffc) << (5 - 2);
case AArch64::fixup_a64_condbr:
// R_AARCH64_CONDBR19: Sets the immediate field of a conditional branch
// instruction to bits 1FFFFC of S+A-P, checking -2^20 <= S+A-P < 2^20.
assert((int64_t)Value >= -(1LL << 20) &&
(int64_t)Value < (1LL << 20) && "Out of range B.cond fixup");
return (Value & 0x1ffffc) << (5 - 2);
case AArch64::fixup_a64_uncondbr:
// R_AARCH64_JUMP26 same as below (except to a linker, possibly).
case AArch64::fixup_a64_call:
// R_AARCH64_CALL26: Sets a CALL immediate field to bits FFFFFFC of S+A-P,
// checking that -2^27 <= S+A-P < 2^27.
assert((int64_t)Value >= -(1LL << 27) &&
(int64_t)Value < (1LL << 27) && "Out of range branch fixup");
return (Value & 0xffffffc) >> 2;
case AArch64::fixup_a64_adr_gottprel_page:
// R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: Set an ADRP immediate field to bits
// 1FFFFF000 of Page(G(TPREL(S+A))) - Page(P); check -2^32 <= X < 2^32.
case AArch64::fixup_a64_tlsdesc_adr_page:
// R_AARCH64_TLSDESC_ADR_PAGE: Set an ADRP immediate field to bits 1FFFFF000
// of Page(G(TLSDESC(S+A))) - Page(P); check -2^32 <= X < 2^32.
case AArch64::fixup_a64_adr_prel_got_page:
// R_AARCH64_ADR_GOT_PAGE: Sets the immediate value of an ADRP to bits
// 1FFFFF000 of the operation, checking that -2^32 < Page(G(S))-Page(GOT) <
// 2^32.
assert((int64_t)Value >= -(1LL << 32) &&
(int64_t)Value < (1LL << 32) && "Out of range ADRP fixup");
return ADRImmBits((Value & 0x1fffff000ULL) >> 12);
case AArch64::fixup_a64_ld64_gottprel_lo12_nc:
// R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: Set an LD offset field to bits FF8
// of X, with no overflow check. Check that X & 7 == 0.
case AArch64::fixup_a64_tlsdesc_ld64_lo12_nc:
// R_AARCH64_TLSDESC_LD64_LO12_NC: Set an LD offset field to bits FF8 of
// G(TLSDESC(S+A)), with no overflow check. Check that X & 7 == 0.
case AArch64::fixup_a64_ld64_got_lo12_nc:
// R_AARCH64_LD64_GOT_LO12_NC: Sets the LD/ST immediate field to bits FF8 of
// G(S) with no overflow check. Check X & 7 == 0
assert(((int64_t)Value & 7) == 0 && "Misaligned fixup");
return (Value & 0xff8) << 7;
case AArch64::fixup_a64_tlsdesc_call:
// R_AARCH64_TLSDESC_CALL: For relaxation only.
return 0;
}
}
MCAsmBackend *
llvm::createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) {
Triple TheTriple(TT);
return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ true);
}
MCAsmBackend *
llvm::createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) {
Triple TheTriple(TT);
return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS(), /*isLittle*/ false);
}

291
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@ -1,291 +0,0 @@
//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file handles ELF-specific object emission, converting LLVM's internal
// fixups into the appropriate relocations.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AArch64FixupKinds.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
namespace {
class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
public:
AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian);
virtual ~AArch64ELFObjectWriter();
protected:
unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel) const override;
private:
};
}
AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsLittleEndian)
: MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
/*HasRelocationAddend*/ true)
{}
AArch64ELFObjectWriter::~AArch64ELFObjectWriter()
{}
unsigned AArch64ELFObjectWriter::GetRelocType(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
unsigned Type;
if (IsPCRel) {
switch ((unsigned)Fixup.getKind()) {
default:
llvm_unreachable("Unimplemented fixup -> relocation");
case FK_Data_8:
return ELF::R_AARCH64_PREL64;
case FK_Data_4:
return ELF::R_AARCH64_PREL32;
case FK_Data_2:
return ELF::R_AARCH64_PREL16;
case AArch64::fixup_a64_ld_prel:
Type = ELF::R_AARCH64_LD_PREL_LO19;
break;
case AArch64::fixup_a64_adr_prel:
Type = ELF::R_AARCH64_ADR_PREL_LO21;
break;
case AArch64::fixup_a64_adr_prel_page:
Type = ELF::R_AARCH64_ADR_PREL_PG_HI21;
break;
case AArch64::fixup_a64_adr_prel_got_page:
Type = ELF::R_AARCH64_ADR_GOT_PAGE;
break;
case AArch64::fixup_a64_tstbr:
Type = ELF::R_AARCH64_TSTBR14;
break;
case AArch64::fixup_a64_condbr:
Type = ELF::R_AARCH64_CONDBR19;
break;
case AArch64::fixup_a64_uncondbr:
Type = ELF::R_AARCH64_JUMP26;
break;
case AArch64::fixup_a64_call:
Type = ELF::R_AARCH64_CALL26;
break;
case AArch64::fixup_a64_adr_gottprel_page:
Type = ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21;
break;
case AArch64::fixup_a64_ld_gottprel_prel19:
Type = ELF::R_AARCH64_TLSIE_LD_GOTTPREL_PREL19;
break;
case AArch64::fixup_a64_tlsdesc_adr_page:
Type = ELF::R_AARCH64_TLSDESC_ADR_PAGE;
break;
}
} else {
switch ((unsigned)Fixup.getKind()) {
default:
llvm_unreachable("Unimplemented fixup -> relocation");
case FK_Data_8:
return ELF::R_AARCH64_ABS64;
case FK_Data_4:
return ELF::R_AARCH64_ABS32;
case FK_Data_2:
return ELF::R_AARCH64_ABS16;
case AArch64::fixup_a64_add_lo12:
Type = ELF::R_AARCH64_ADD_ABS_LO12_NC;
break;
case AArch64::fixup_a64_ld64_got_lo12_nc:
Type = ELF::R_AARCH64_LD64_GOT_LO12_NC;
break;
case AArch64::fixup_a64_ldst8_lo12:
Type = ELF::R_AARCH64_LDST8_ABS_LO12_NC;
break;
case AArch64::fixup_a64_ldst16_lo12:
Type = ELF::R_AARCH64_LDST16_ABS_LO12_NC;
break;
case AArch64::fixup_a64_ldst32_lo12:
Type = ELF::R_AARCH64_LDST32_ABS_LO12_NC;
break;
case AArch64::fixup_a64_ldst64_lo12:
Type = ELF::R_AARCH64_LDST64_ABS_LO12_NC;
break;
case AArch64::fixup_a64_ldst128_lo12:
Type = ELF::R_AARCH64_LDST128_ABS_LO12_NC;
break;
case AArch64::fixup_a64_movw_uabs_g0:
Type = ELF::R_AARCH64_MOVW_UABS_G0;
break;
case AArch64::fixup_a64_movw_uabs_g0_nc:
Type = ELF::R_AARCH64_MOVW_UABS_G0_NC;
break;
case AArch64::fixup_a64_movw_uabs_g1:
Type = ELF::R_AARCH64_MOVW_UABS_G1;
break;
case AArch64::fixup_a64_movw_uabs_g1_nc:
Type = ELF::R_AARCH64_MOVW_UABS_G1_NC;
break;
case AArch64::fixup_a64_movw_uabs_g2:
Type = ELF::R_AARCH64_MOVW_UABS_G2;
break;
case AArch64::fixup_a64_movw_uabs_g2_nc:
Type = ELF::R_AARCH64_MOVW_UABS_G2_NC;
break;
case AArch64::fixup_a64_movw_uabs_g3:
Type = ELF::R_AARCH64_MOVW_UABS_G3;
break;
case AArch64::fixup_a64_movw_sabs_g0:
Type = ELF::R_AARCH64_MOVW_SABS_G0;
break;
case AArch64::fixup_a64_movw_sabs_g1:
Type = ELF::R_AARCH64_MOVW_SABS_G1;
break;
case AArch64::fixup_a64_movw_sabs_g2:
Type = ELF::R_AARCH64_MOVW_SABS_G2;
break;
// TLS Local-dynamic block
case AArch64::fixup_a64_movw_dtprel_g2:
Type = ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
break;
case AArch64::fixup_a64_movw_dtprel_g1:
Type = ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1;
break;
case AArch64::fixup_a64_movw_dtprel_g1_nc:
Type = ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
break;
case AArch64::fixup_a64_movw_dtprel_g0:
Type = ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0;
break;
case AArch64::fixup_a64_movw_dtprel_g0_nc:
Type = ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC;
break;
case AArch64::fixup_a64_add_dtprel_hi12:
Type = ELF::R_AARCH64_TLSLD_ADD_DTPREL_HI12;
break;
case AArch64::fixup_a64_add_dtprel_lo12:
Type = ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12;
break;
case AArch64::fixup_a64_add_dtprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst8_dtprel_lo12:
Type = ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12;
break;
case AArch64::fixup_a64_ldst8_dtprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst16_dtprel_lo12:
Type = ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12;
break;
case AArch64::fixup_a64_ldst16_dtprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst32_dtprel_lo12:
Type = ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12;
break;
case AArch64::fixup_a64_ldst32_dtprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst64_dtprel_lo12:
Type = ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12;
break;
case AArch64::fixup_a64_ldst64_dtprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC;
break;
// TLS initial-exec block
case AArch64::fixup_a64_movw_gottprel_g1:
Type = ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
break;
case AArch64::fixup_a64_movw_gottprel_g0_nc:
Type = ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
break;
case AArch64::fixup_a64_ld64_gottprel_lo12_nc:
Type = ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
break;
// TLS local-exec block
case AArch64::fixup_a64_movw_tprel_g2:
Type = ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
break;
case AArch64::fixup_a64_movw_tprel_g1:
Type = ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1;
break;
case AArch64::fixup_a64_movw_tprel_g1_nc:
Type = ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
break;
case AArch64::fixup_a64_movw_tprel_g0:
Type = ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0;
break;
case AArch64::fixup_a64_movw_tprel_g0_nc:
Type = ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC;
break;
case AArch64::fixup_a64_add_tprel_hi12:
Type = ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12;
break;
case AArch64::fixup_a64_add_tprel_lo12:
Type = ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12;
break;
case AArch64::fixup_a64_add_tprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst8_tprel_lo12:
Type = ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12;
break;
case AArch64::fixup_a64_ldst8_tprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst16_tprel_lo12:
Type = ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12;
break;
case AArch64::fixup_a64_ldst16_tprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst32_tprel_lo12:
Type = ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12;
break;
case AArch64::fixup_a64_ldst32_tprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC;
break;
case AArch64::fixup_a64_ldst64_tprel_lo12:
Type = ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12;
break;
case AArch64::fixup_a64_ldst64_tprel_lo12_nc:
Type = ELF::R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC;
break;
// TLS general-dynamic block
case AArch64::fixup_a64_tlsdesc_adr_page:
Type = ELF::R_AARCH64_TLSDESC_ADR_PAGE;
break;
case AArch64::fixup_a64_tlsdesc_ld64_lo12_nc:
Type = ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
break;
case AArch64::fixup_a64_tlsdesc_add_lo12_nc:
Type = ELF::R_AARCH64_TLSDESC_ADD_LO12_NC;
break;
case AArch64::fixup_a64_tlsdesc_call:
Type = ELF::R_AARCH64_TLSDESC_CALL;
break;
}
}
return Type;
}
MCObjectWriter *llvm::createAArch64ELFObjectWriter(raw_ostream &OS,
uint8_t OSABI,
bool IsLittleEndian) {
MCELFObjectTargetWriter *MOTW = new AArch64ELFObjectWriter(OSABI, IsLittleEndian);
return createELFObjectWriter(MOTW, OS, IsLittleEndian);
}

161
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@ -1,161 +0,0 @@
//===- lib/MC/AArch64ELFStreamer.cpp - ELF Object Output for AArch64 ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file assembles .s files and emits AArch64 ELF .o object files. Different
// from generic ELF streamer in emitting mapping symbols ($x and $d) to delimit
// regions of data and code.
//
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELF.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCELFSymbolFlags.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCObjectStreamer.h"
#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
/// Extend the generic ELFStreamer class so that it can emit mapping symbols at
/// the appropriate points in the object files. These symbols are defined in the
/// AArch64 ELF ABI:
/// infocenter.arm.com/help/topic/com.arm.doc.ihi0056a/IHI0056A_aaelf64.pdf
///
/// In brief: $x or $d should be emitted at the start of each contiguous region
/// of A64 code or data in a section. In practice, this emission does not rely
/// on explicit assembler directives but on inherent properties of the
/// directives doing the emission (e.g. ".byte" is data, "add x0, x0, x0" an
/// instruction).
///
/// As a result this system is orthogonal to the DataRegion infrastructure used
/// by MachO. Beware!
class AArch64ELFStreamer : public MCELFStreamer {
public:
AArch64ELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS,
MCCodeEmitter *Emitter)
: MCELFStreamer(Context, TAB, OS, Emitter), MappingSymbolCounter(0),
LastEMS(EMS_None) {}
~AArch64ELFStreamer() {}
void ChangeSection(const MCSection *Section,
const MCExpr *Subsection) override {
// We have to keep track of the mapping symbol state of any sections we
// use. Each one should start off as EMS_None, which is provided as the
// default constructor by DenseMap::lookup.
LastMappingSymbols[getPreviousSection().first] = LastEMS;
LastEMS = LastMappingSymbols.lookup(Section);
MCELFStreamer::ChangeSection(Section, Subsection);
}
/// This function is the one used to emit instruction data into the ELF
/// streamer. We override it to add the appropriate mapping symbol if
/// necessary.
void EmitInstruction(const MCInst& Inst,
const MCSubtargetInfo &STI) override {
EmitA64MappingSymbol();
MCELFStreamer::EmitInstruction(Inst, STI);
}
/// This is one of the functions used to emit data into an ELF section, so the
/// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
/// if necessary.
void EmitBytes(StringRef Data) override {
EmitDataMappingSymbol();
MCELFStreamer::EmitBytes(Data);
}
/// This is one of the functions used to emit data into an ELF section, so the
/// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
/// if necessary.
void EmitValueImpl(const MCExpr *Value, unsigned Size,
const SMLoc &Loc) override {
EmitDataMappingSymbol();
MCELFStreamer::EmitValueImpl(Value, Size, Loc);
}
private:
enum ElfMappingSymbol {
EMS_None,
EMS_A64,
EMS_Data
};
void EmitDataMappingSymbol() {
if (LastEMS == EMS_Data) return;
EmitMappingSymbol("$d");
LastEMS = EMS_Data;
}
void EmitA64MappingSymbol() {
if (LastEMS == EMS_A64) return;
EmitMappingSymbol("$x");
LastEMS = EMS_A64;
}
void EmitMappingSymbol(StringRef Name) {
MCSymbol *Start = getContext().CreateTempSymbol();
EmitLabel(Start);
MCSymbol *Symbol =
getContext().GetOrCreateSymbol(Name + "." +
Twine(MappingSymbolCounter++));
MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
MCELF::SetType(SD, ELF::STT_NOTYPE);
MCELF::SetBinding(SD, ELF::STB_LOCAL);
SD.setExternal(false);
AssignSection(Symbol, getCurrentSection().first);
const MCExpr *Value = MCSymbolRefExpr::Create(Start, getContext());
Symbol->setVariableValue(Value);
}
int64_t MappingSymbolCounter;
DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
ElfMappingSymbol LastEMS;
/// @}
};
}
namespace llvm {
MCELFStreamer* createAArch64ELFStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *Emitter,
bool RelaxAll, bool NoExecStack) {
AArch64ELFStreamer *S = new AArch64ELFStreamer(Context, TAB, OS, Emitter);
if (RelaxAll)
S->getAssembler().setRelaxAll(true);
if (NoExecStack)
S->getAssembler().setNoExecStack(true);
return S;
}
}

27
lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h
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@ -1,27 +0,0 @@
//===-- AArch64ELFStreamer.h - ELF Streamer for AArch64 ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements ELF streamer information for the AArch64 backend.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64_ELF_STREAMER_H
#define LLVM_AARCH64_ELF_STREAMER_H
#include "llvm/MC/MCELFStreamer.h"
namespace llvm {
MCELFStreamer* createAArch64ELFStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS,
MCCodeEmitter *Emitter,
bool RelaxAll, bool NoExecStack);
}
#endif // AArch64_ELF_STREAMER_H

113
lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
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@ -1,113 +0,0 @@
//=- AArch64/AArch64FixupKinds.h - AArch64 Specific Fixup Entries -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the LLVM fixups applied to MCInsts in the AArch64
// backend.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64_AARCH64FIXUPKINDS_H
#define LLVM_AARCH64_AARCH64FIXUPKINDS_H
#include "llvm/MC/MCFixup.h"
namespace llvm {
namespace AArch64 {
enum Fixups {
fixup_a64_ld_prel = FirstTargetFixupKind,
fixup_a64_adr_prel,
fixup_a64_adr_prel_page,
fixup_a64_add_lo12,
fixup_a64_ldst8_lo12,
fixup_a64_ldst16_lo12,
fixup_a64_ldst32_lo12,
fixup_a64_ldst64_lo12,
fixup_a64_ldst128_lo12,
fixup_a64_tstbr,
fixup_a64_condbr,
fixup_a64_uncondbr,
fixup_a64_call,
fixup_a64_movw_uabs_g0,
fixup_a64_movw_uabs_g0_nc,
fixup_a64_movw_uabs_g1,
fixup_a64_movw_uabs_g1_nc,
fixup_a64_movw_uabs_g2,
fixup_a64_movw_uabs_g2_nc,
fixup_a64_movw_uabs_g3,
fixup_a64_movw_sabs_g0,
fixup_a64_movw_sabs_g1,
fixup_a64_movw_sabs_g2,
fixup_a64_adr_prel_got_page,
fixup_a64_ld64_got_lo12_nc,
// Produce offsets relative to the module's dynamic TLS area.
fixup_a64_movw_dtprel_g2,
fixup_a64_movw_dtprel_g1,
fixup_a64_movw_dtprel_g1_nc,
fixup_a64_movw_dtprel_g0,
fixup_a64_movw_dtprel_g0_nc,
fixup_a64_add_dtprel_hi12,
fixup_a64_add_dtprel_lo12,
fixup_a64_add_dtprel_lo12_nc,
fixup_a64_ldst8_dtprel_lo12,
fixup_a64_ldst8_dtprel_lo12_nc,
fixup_a64_ldst16_dtprel_lo12,
fixup_a64_ldst16_dtprel_lo12_nc,
fixup_a64_ldst32_dtprel_lo12,
fixup_a64_ldst32_dtprel_lo12_nc,
fixup_a64_ldst64_dtprel_lo12,
fixup_a64_ldst64_dtprel_lo12_nc,
// Produce the GOT entry containing a variable's address in TLS's
// initial-exec mode.
fixup_a64_movw_gottprel_g1,
fixup_a64_movw_gottprel_g0_nc,
fixup_a64_adr_gottprel_page,
fixup_a64_ld64_gottprel_lo12_nc,
fixup_a64_ld_gottprel_prel19,
// Produce offsets relative to the thread pointer: TPIDR_EL0.
fixup_a64_movw_tprel_g2,
fixup_a64_movw_tprel_g1,
fixup_a64_movw_tprel_g1_nc,
fixup_a64_movw_tprel_g0,
fixup_a64_movw_tprel_g0_nc,
fixup_a64_add_tprel_hi12,
fixup_a64_add_tprel_lo12,
fixup_a64_add_tprel_lo12_nc,
fixup_a64_ldst8_tprel_lo12,
fixup_a64_ldst8_tprel_lo12_nc,
fixup_a64_ldst16_tprel_lo12,
fixup_a64_ldst16_tprel_lo12_nc,
fixup_a64_ldst32_tprel_lo12,
fixup_a64_ldst32_tprel_lo12_nc,
fixup_a64_ldst64_tprel_lo12,
fixup_a64_ldst64_tprel_lo12_nc,
// Produce the special fixups used by the general-dynamic TLS model.
fixup_a64_tlsdesc_adr_page,
fixup_a64_tlsdesc_ld64_lo12_nc,
fixup_a64_tlsdesc_add_lo12_nc,
fixup_a64_tlsdesc_call,
// Marker
LastTargetFixupKind,
NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
}
}
#endif

46
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
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@ -1,46 +0,0 @@
//===-- AArch64MCAsmInfo.cpp - AArch64 asm properties ---------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declarations of the AArch64MCAsmInfo properties.
//
//===----------------------------------------------------------------------===//
#include "AArch64MCAsmInfo.h"
#include "llvm/ADT/Triple.h"
using namespace llvm;
AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo(StringRef TT) {
Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::aarch64_be)
IsLittleEndian = false;
PointerSize = 8;
// ".comm align is in bytes but .align is pow-2."
AlignmentIsInBytes = false;
CommentString = "//";
Code32Directive = ".code\t32";
Data16bitsDirective = "\t.hword\t";
Data32bitsDirective = "\t.word\t";
Data64bitsDirective = "\t.xword\t";
HasLEB128 = true;
SupportsDebugInformation = true;
// Exceptions handling
ExceptionsType = ExceptionHandling::DwarfCFI;
UseIntegratedAssembler = true;
}
// Pin the vtable to this file.
void AArch64ELFMCAsmInfo::anchor() {}

29
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
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@ -1,29 +0,0 @@
//==-- AArch64MCAsmInfo.h - AArch64 asm properties -------------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the AArch64MCAsmInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64TARGETASMINFO_H
#define LLVM_AARCH64TARGETASMINFO_H
#include "llvm/MC/MCAsmInfoELF.h"
namespace llvm {
struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
explicit AArch64ELFMCAsmInfo(StringRef TT);
private:
void anchor() override;
};
} // namespace llvm
#endif

613
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -1,613 +0,0 @@
//=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code =//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the AArch64MCCodeEmitter class.
//
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AArch64FixupKinds.h"
#include "MCTargetDesc/AArch64MCExpr.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "mccodeemitter"
namespace {
class AArch64MCCodeEmitter : public MCCodeEmitter {
AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION;
void operator=(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION;
MCContext &Ctx;
public:
AArch64MCCodeEmitter(MCContext &ctx) : Ctx(ctx) {}
~AArch64MCCodeEmitter() {}
unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
template<int MemSize>
unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return getOffsetUImm12OpValue(MI, OpIdx, Fixups, STI, MemSize);
}
unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI,
int MemSize) const;
unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm8(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm16(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm32(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftRightImm64(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm8(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm16(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm32(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getShiftLeftImm64(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// Labels are handled mostly the same way: a symbol is needed, and
// just gets some fixup attached.
template<AArch64::Fixups fixupDesired>
unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getAddressWithFixup(const MCOperand &MO,
unsigned FixupKind,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
void EmitByte(unsigned char C, raw_ostream &OS) const {
OS << (char)C;
}
void EmitInstruction(uint32_t Val, raw_ostream &OS) const {
// Output the constant in little endian byte order.
for (unsigned i = 0; i != 4; ++i) {
EmitByte(Val & 0xff, OS);
Val >>= 8;
}
}
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
template<int hasRs, int hasRt2> unsigned
fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO,
unsigned FixupKind,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (!MO.isExpr()) {
// This can occur for manually decoded or constructed MCInsts, but neither
// the assembly-parser nor instruction selection will currently produce an
// MCInst that's not a symbol reference.
assert(MO.isImm() && "Unexpected address requested");
return MO.getImm();
}
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(FixupKind);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
return 0;
}
unsigned AArch64MCCodeEmitter::
getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI,
int MemSize) const {
const MCOperand &ImmOp = MI.getOperand(OpIdx);
if (ImmOp.isImm())
return ImmOp.getImm();
assert(ImmOp.isExpr() && "Unexpected operand type");
const AArch64MCExpr *Expr = cast<AArch64MCExpr>(ImmOp.getExpr());
unsigned FixupKind;
switch (Expr->getKind()) {
default: llvm_unreachable("Unexpected operand modifier");
case AArch64MCExpr::VK_AARCH64_LO12: {
static const unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_lo12,
AArch64::fixup_a64_ldst16_lo12,
AArch64::fixup_a64_ldst32_lo12,
AArch64::fixup_a64_ldst64_lo12,
AArch64::fixup_a64_ldst128_lo12 };
assert(MemSize <= 16 && "Invalid fixup for operation");
FixupKind = FixupsBySize[Log2_32(MemSize)];
break;
}
case AArch64MCExpr::VK_AARCH64_GOT_LO12:
assert(MemSize == 8 && "Invalid fixup for operation");
FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc;
break;
case AArch64MCExpr::VK_AARCH64_DTPREL_LO12: {
static const unsigned FixupsBySize[] = {
AArch64::fixup_a64_ldst8_dtprel_lo12,
AArch64::fixup_a64_ldst16_dtprel_lo12,
AArch64::fixup_a64_ldst32_dtprel_lo12,
AArch64::fixup_a64_ldst64_dtprel_lo12
};
assert(MemSize <= 8 && "Invalid fixup for operation");
FixupKind = FixupsBySize[Log2_32(MemSize)];
break;
}
case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC: {
static const unsigned FixupsBySize[] = {
AArch64::fixup_a64_ldst8_dtprel_lo12_nc,
AArch64::fixup_a64_ldst16_dtprel_lo12_nc,
AArch64::fixup_a64_ldst32_dtprel_lo12_nc,
AArch64::fixup_a64_ldst64_dtprel_lo12_nc
};
assert(MemSize <= 8 && "Invalid fixup for operation");
FixupKind = FixupsBySize[Log2_32(MemSize)];
break;
}
case AArch64MCExpr::VK_AARCH64_GOTTPREL_LO12:
assert(MemSize == 8 && "Invalid fixup for operation");
FixupKind = AArch64::fixup_a64_ld64_gottprel_lo12_nc;
break;
case AArch64MCExpr::VK_AARCH64_TPREL_LO12:{
static const unsigned FixupsBySize[] = {
AArch64::fixup_a64_ldst8_tprel_lo12,
AArch64::fixup_a64_ldst16_tprel_lo12,
AArch64::fixup_a64_ldst32_tprel_lo12,
AArch64::fixup_a64_ldst64_tprel_lo12
};
assert(MemSize <= 8 && "Invalid fixup for operation");
FixupKind = FixupsBySize[Log2_32(MemSize)];
break;
}
case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC: {
static const unsigned FixupsBySize[] = {
AArch64::fixup_a64_ldst8_tprel_lo12_nc,
AArch64::fixup_a64_ldst16_tprel_lo12_nc,
AArch64::fixup_a64_ldst32_tprel_lo12_nc,
AArch64::fixup_a64_ldst64_tprel_lo12_nc
};
assert(MemSize <= 8 && "Invalid fixup for operation");
FixupKind = FixupsBySize[Log2_32(MemSize)];
break;
}
case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12:
assert(MemSize == 8 && "Invalid fixup for operation");
FixupKind = AArch64::fixup_a64_tlsdesc_ld64_lo12_nc;
break;
}
return getAddressWithFixup(ImmOp, FixupKind, Fixups, STI);
}
unsigned
AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
assert(MO.isExpr());
unsigned FixupKind = 0;
switch(cast<AArch64MCExpr>(MO.getExpr())->getKind()) {
default: llvm_unreachable("Invalid expression modifier");
case AArch64MCExpr::VK_AARCH64_LO12:
FixupKind = AArch64::fixup_a64_add_lo12; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_HI12:
FixupKind = AArch64::fixup_a64_add_dtprel_hi12; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_LO12:
FixupKind = AArch64::fixup_a64_add_dtprel_lo12; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC:
FixupKind = AArch64::fixup_a64_add_dtprel_lo12_nc; break;
case AArch64MCExpr::VK_AARCH64_TPREL_HI12:
FixupKind = AArch64::fixup_a64_add_tprel_hi12; break;
case AArch64MCExpr::VK_AARCH64_TPREL_LO12:
FixupKind = AArch64::fixup_a64_add_tprel_lo12; break;
case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC:
FixupKind = AArch64::fixup_a64_add_tprel_lo12_nc; break;
case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12:
FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break;
}
return getAddressWithFixup(MO, FixupKind, Fixups, STI);
}
unsigned
AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
assert(MO.isExpr());
unsigned Modifier = AArch64MCExpr::VK_AARCH64_None;
if (const AArch64MCExpr *Expr = dyn_cast<AArch64MCExpr>(MO.getExpr()))
Modifier = Expr->getKind();
unsigned FixupKind = 0;
switch(Modifier) {
case AArch64MCExpr::VK_AARCH64_None:
FixupKind = AArch64::fixup_a64_adr_prel_page;
break;
case AArch64MCExpr::VK_AARCH64_GOT:
FixupKind = AArch64::fixup_a64_adr_prel_got_page;
break;
case AArch64MCExpr::VK_AARCH64_GOTTPREL:
FixupKind = AArch64::fixup_a64_adr_gottprel_page;
break;
case AArch64MCExpr::VK_AARCH64_TLSDESC:
FixupKind = AArch64::fixup_a64_tlsdesc_adr_page;
break;
default:
llvm_unreachable("Unknown symbol reference kind for ADRP instruction");
}
return getAddressWithFixup(MO, FixupKind, Fixups, STI);
}
unsigned
AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
assert(MO.isImm() && "Only immediate expected for shift");
return ((32 - MO.getImm()) & 0x1f) | (31 - MO.getImm()) << 6;
}
unsigned
AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
assert(MO.isImm() && "Only immediate expected for shift");
return ((64 - MO.getImm()) & 0x3f) | (63 - MO.getImm()) << 6;
}
unsigned AArch64MCCodeEmitter::getShiftRightImm8(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 8 - MI.getOperand(Op).getImm();
}
unsigned AArch64MCCodeEmitter::getShiftRightImm16(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 16 - MI.getOperand(Op).getImm();
}
unsigned AArch64MCCodeEmitter::getShiftRightImm32(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 32 - MI.getOperand(Op).getImm();
}
unsigned AArch64MCCodeEmitter::getShiftRightImm64(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return 64 - MI.getOperand(Op).getImm();
}
unsigned AArch64MCCodeEmitter::getShiftLeftImm8(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 8;
}
unsigned AArch64MCCodeEmitter::getShiftLeftImm16(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 16;
}
unsigned AArch64MCCodeEmitter::getShiftLeftImm32(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 32;
}
unsigned AArch64MCCodeEmitter::getShiftLeftImm64(
const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
return MI.getOperand(Op).getImm() - 64;
}
template<AArch64::Fixups fixupDesired> unsigned
AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI,
unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isExpr())
return getAddressWithFixup(MO, fixupDesired, Fixups, STI);
assert(MO.isImm());
return MO.getImm();
}
unsigned
AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI,
unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpIdx);
if (MO.isImm())
return MO.getImm();
assert(MO.isExpr());
unsigned FixupKind;
if (isa<AArch64MCExpr>(MO.getExpr())) {
assert(dyn_cast<AArch64MCExpr>(MO.getExpr())->getKind()
== AArch64MCExpr::VK_AARCH64_GOTTPREL
&& "Invalid symbol modifier for literal load");
FixupKind = AArch64::fixup_a64_ld_gottprel_prel19;
} else {
FixupKind = AArch64::fixup_a64_ld_prel;
}
return getAddressWithFixup(MO, FixupKind, Fixups, STI);
}
unsigned
AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) {
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
}
llvm_unreachable("Unable to encode MCOperand!");
return 0;
}
unsigned
AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &UImm16MO = MI.getOperand(OpIdx);
const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
unsigned Result = static_cast<unsigned>(ShiftMO.getImm()) << 16;
if (UImm16MO.isImm()) {
Result |= UImm16MO.getImm();
return Result;
}
const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
AArch64::Fixups requestedFixup;
switch (A64E->getKind()) {
default: llvm_unreachable("unexpected expression modifier");
case AArch64MCExpr::VK_AARCH64_ABS_G0:
requestedFixup = AArch64::fixup_a64_movw_uabs_g0; break;
case AArch64MCExpr::VK_AARCH64_ABS_G0_NC:
requestedFixup = AArch64::fixup_a64_movw_uabs_g0_nc; break;
case AArch64MCExpr::VK_AARCH64_ABS_G1:
requestedFixup = AArch64::fixup_a64_movw_uabs_g1; break;
case AArch64MCExpr::VK_AARCH64_ABS_G1_NC:
requestedFixup = AArch64::fixup_a64_movw_uabs_g1_nc; break;
case AArch64MCExpr::VK_AARCH64_ABS_G2:
requestedFixup = AArch64::fixup_a64_movw_uabs_g2; break;
case AArch64MCExpr::VK_AARCH64_ABS_G2_NC:
requestedFixup = AArch64::fixup_a64_movw_uabs_g2_nc; break;
case AArch64MCExpr::VK_AARCH64_ABS_G3:
requestedFixup = AArch64::fixup_a64_movw_uabs_g3; break;
case AArch64MCExpr::VK_AARCH64_SABS_G0:
requestedFixup = AArch64::fixup_a64_movw_sabs_g0; break;
case AArch64MCExpr::VK_AARCH64_SABS_G1:
requestedFixup = AArch64::fixup_a64_movw_sabs_g1; break;
case AArch64MCExpr::VK_AARCH64_SABS_G2:
requestedFixup = AArch64::fixup_a64_movw_sabs_g2; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
requestedFixup = AArch64::fixup_a64_movw_dtprel_g2; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
requestedFixup = AArch64::fixup_a64_movw_dtprel_g1; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC:
requestedFixup = AArch64::fixup_a64_movw_dtprel_g1_nc; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
requestedFixup = AArch64::fixup_a64_movw_dtprel_g0; break;
case AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC:
requestedFixup = AArch64::fixup_a64_movw_dtprel_g0_nc; break;
case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
requestedFixup = AArch64::fixup_a64_movw_gottprel_g1; break;
case AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC:
requestedFixup = AArch64::fixup_a64_movw_gottprel_g0_nc; break;
case AArch64MCExpr::VK_AARCH64_TPREL_G2:
requestedFixup = AArch64::fixup_a64_movw_tprel_g2; break;
case AArch64MCExpr::VK_AARCH64_TPREL_G1:
requestedFixup = AArch64::fixup_a64_movw_tprel_g1; break;
case AArch64MCExpr::VK_AARCH64_TPREL_G1_NC:
requestedFixup = AArch64::fixup_a64_movw_tprel_g1_nc; break;
case AArch64MCExpr::VK_AARCH64_TPREL_G0:
requestedFixup = AArch64::fixup_a64_movw_tprel_g0; break;
case AArch64MCExpr::VK_AARCH64_TPREL_G0_NC:
requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break;
}
return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups, STI);
}
template<int hasRs, int hasRt2> unsigned
AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
if (!hasRs) EncodedValue |= 0x001F0000;
if (!hasRt2) EncodedValue |= 0x00007C00;
return EncodedValue;
}
unsigned
AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
// If one of the signed fixup kinds is applied to a MOVZ instruction, the
// eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
// job to ensure that any bits possibly affected by this are 0. This means we
// must zero out bit 30 (essentially emitting a MOVN).
MCOperand UImm16MO = MI.getOperand(1);
// Nothing to do if there's no fixup.
if (UImm16MO.isImm())
return EncodedValue;
const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
switch (A64E->getKind()) {
case AArch64MCExpr::VK_AARCH64_SABS_G0:
case AArch64MCExpr::VK_AARCH64_SABS_G1:
case AArch64MCExpr::VK_AARCH64_SABS_G2:
case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
case AArch64MCExpr::VK_AARCH64_TPREL_G2:
case AArch64MCExpr::VK_AARCH64_TPREL_G1:
case AArch64MCExpr::VK_AARCH64_TPREL_G0:
return EncodedValue & ~(1u << 30);
default:
// Nothing to do for an unsigned fixup.
return EncodedValue;
}
llvm_unreachable("Should have returned by now");
}
unsigned
AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
unsigned EncodedValue,
const MCSubtargetInfo &STI) const {
// The Ra field of SMULH and UMULH is unused: it should be assembled as 31
// (i.e. all bits 1) but is ignored by the processor.
EncodedValue |= 0x1f << 10;
return EncodedValue;
}
MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new AArch64MCCodeEmitter(Ctx);
}
void AArch64MCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
// This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
// following (BLR) instruction. It doesn't emit any code itself so it
// doesn't go through the normal TableGenerated channels.
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_a64_tlsdesc_call);
const MCExpr *Expr;
Expr = AArch64MCExpr::CreateTLSDesc(MI.getOperand(0).getExpr(), Ctx);
Fixups.push_back(MCFixup::Create(0, Expr, Fixup));
return;
}
uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
EmitInstruction(Binary, OS);
}
#include "AArch64GenMCCodeEmitter.inc"

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@ -1,179 +0,0 @@
//===-- AArch64MCExpr.cpp - AArch64 specific MC expression classes --------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the implementation of the assembly expression modifiers
// accepted by the AArch64 architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
//
//===----------------------------------------------------------------------===//
#include "AArch64MCExpr.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELF.h"
#include "llvm/Object/ELF.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64mcexpr"
const AArch64MCExpr*
AArch64MCExpr::Create(VariantKind Kind, const MCExpr *Expr,
MCContext &Ctx) {
return new (Ctx) AArch64MCExpr(Kind, Expr);
}
void AArch64MCExpr::PrintImpl(raw_ostream &OS) const {
switch (Kind) {
default: llvm_unreachable("Invalid kind!");
case VK_AARCH64_GOT: OS << ":got:"; break;
case VK_AARCH64_GOT_LO12: OS << ":got_lo12:"; break;
case VK_AARCH64_LO12: OS << ":lo12:"; break;
case VK_AARCH64_ABS_G0: OS << ":abs_g0:"; break;
case VK_AARCH64_ABS_G0_NC: OS << ":abs_g0_nc:"; break;
case VK_AARCH64_ABS_G1: OS << ":abs_g1:"; break;
case VK_AARCH64_ABS_G1_NC: OS << ":abs_g1_nc:"; break;
case VK_AARCH64_ABS_G2: OS << ":abs_g2:"; break;
case VK_AARCH64_ABS_G2_NC: OS << ":abs_g2_nc:"; break;
case VK_AARCH64_ABS_G3: OS << ":abs_g3:"; break;
case VK_AARCH64_SABS_G0: OS << ":abs_g0_s:"; break;
case VK_AARCH64_SABS_G1: OS << ":abs_g1_s:"; break;
case VK_AARCH64_SABS_G2: OS << ":abs_g2_s:"; break;
case VK_AARCH64_DTPREL_G2: OS << ":dtprel_g2:"; break;
case VK_AARCH64_DTPREL_G1: OS << ":dtprel_g1:"; break;
case VK_AARCH64_DTPREL_G1_NC: OS << ":dtprel_g1_nc:"; break;
case VK_AARCH64_DTPREL_G0: OS << ":dtprel_g0:"; break;
case VK_AARCH64_DTPREL_G0_NC: OS << ":dtprel_g0_nc:"; break;
case VK_AARCH64_DTPREL_HI12: OS << ":dtprel_hi12:"; break;
case VK_AARCH64_DTPREL_LO12: OS << ":dtprel_lo12:"; break;
case VK_AARCH64_DTPREL_LO12_NC: OS << ":dtprel_lo12_nc:"; break;
case VK_AARCH64_GOTTPREL_G1: OS << ":gottprel_g1:"; break;
case VK_AARCH64_GOTTPREL_G0_NC: OS << ":gottprel_g0_nc:"; break;
case VK_AARCH64_GOTTPREL: OS << ":gottprel:"; break;
case VK_AARCH64_GOTTPREL_LO12: OS << ":gottprel_lo12:"; break;
case VK_AARCH64_TPREL_G2: OS << ":tprel_g2:"; break;
case VK_AARCH64_TPREL_G1: OS << ":tprel_g1:"; break;
case VK_AARCH64_TPREL_G1_NC: OS << ":tprel_g1_nc:"; break;
case VK_AARCH64_TPREL_G0: OS << ":tprel_g0:"; break;
case VK_AARCH64_TPREL_G0_NC: OS << ":tprel_g0_nc:"; break;
case VK_AARCH64_TPREL_HI12: OS << ":tprel_hi12:"; break;
case VK_AARCH64_TPREL_LO12: OS << ":tprel_lo12:"; break;
case VK_AARCH64_TPREL_LO12_NC: OS << ":tprel_lo12_nc:"; break;
case VK_AARCH64_TLSDESC: OS << ":tlsdesc:"; break;
case VK_AARCH64_TLSDESC_LO12: OS << ":tlsdesc_lo12:"; break;
}
const MCExpr *Expr = getSubExpr();
if (Expr->getKind() != MCExpr::SymbolRef)
OS << '(';
Expr->print(OS);
if (Expr->getKind() != MCExpr::SymbolRef)
OS << ')';
}
bool
AArch64MCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const {
return getSubExpr()->EvaluateAsRelocatable(Res, Layout);
}
static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {
switch (Expr->getKind()) {
case MCExpr::Target:
llvm_unreachable("Can't handle nested target expression");
break;
case MCExpr::Constant:
break;
case MCExpr::Binary: {
const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm);
fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm);
break;
}
case MCExpr::SymbolRef: {
// We're known to be under a TLS fixup, so any symbol should be
// modified. There should be only one.
const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
MCSymbolData &SD = Asm.getOrCreateSymbolData(SymRef.getSymbol());
MCELF::SetType(SD, ELF::STT_TLS);
break;
}
case MCExpr::Unary:
fixELFSymbolsInTLSFixupsImpl(cast<MCUnaryExpr>(Expr)->getSubExpr(), Asm);
break;
}
}
void AArch64MCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
switch (getKind()) {
default:
return;
case VK_AARCH64_DTPREL_G2:
case VK_AARCH64_DTPREL_G1:
case VK_AARCH64_DTPREL_G1_NC:
case VK_AARCH64_DTPREL_G0:
case VK_AARCH64_DTPREL_G0_NC:
case VK_AARCH64_DTPREL_HI12:
case VK_AARCH64_DTPREL_LO12:
case VK_AARCH64_DTPREL_LO12_NC:
case VK_AARCH64_GOTTPREL_G1:
case VK_AARCH64_GOTTPREL_G0_NC:
case VK_AARCH64_GOTTPREL:
case VK_AARCH64_GOTTPREL_LO12:
case VK_AARCH64_TPREL_G2:
case VK_AARCH64_TPREL_G1:
case VK_AARCH64_TPREL_G1_NC:
case VK_AARCH64_TPREL_G0:
case VK_AARCH64_TPREL_G0_NC:
case VK_AARCH64_TPREL_HI12:
case VK_AARCH64_TPREL_LO12:
case VK_AARCH64_TPREL_LO12_NC:
case VK_AARCH64_TLSDESC:
case VK_AARCH64_TLSDESC_LO12:
break;
}
fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm);
}
// FIXME: This basically copies MCObjectStreamer::AddValueSymbols. Perhaps
// that method should be made public?
// FIXME: really do above: now that two backends are using it.
static void AddValueSymbolsImpl(const MCExpr *Value, MCAssembler *Asm) {
switch (Value->getKind()) {
case MCExpr::Target:
llvm_unreachable("Can't handle nested target expr!");
break;
case MCExpr::Constant:
break;
case MCExpr::Binary: {
const MCBinaryExpr *BE = cast<MCBinaryExpr>(Value);
AddValueSymbolsImpl(BE->getLHS(), Asm);
AddValueSymbolsImpl(BE->getRHS(), Asm);
break;
}
case MCExpr::SymbolRef:
Asm->getOrCreateSymbolData(cast<MCSymbolRefExpr>(Value)->getSymbol());
break;
case MCExpr::Unary:
AddValueSymbolsImpl(cast<MCUnaryExpr>(Value)->getSubExpr(), Asm);
break;
}
}
void AArch64MCExpr::AddValueSymbols(MCAssembler *Asm) const {
AddValueSymbolsImpl(getSubExpr(), Asm);
}

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@ -1,187 +0,0 @@
//==- AArch64MCExpr.h - AArch64 specific MC expression classes --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes AArch64-specific MCExprs, used for modifiers like
// ":lo12:" or ":gottprel_g1:".
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64MCEXPR_H
#define LLVM_AARCH64MCEXPR_H
#include "llvm/MC/MCExpr.h"
namespace llvm {
class AArch64MCExpr : public MCTargetExpr {
public:
enum VariantKind {
VK_AARCH64_None,
VK_AARCH64_GOT, // :got: modifier in assembly
VK_AARCH64_GOT_LO12, // :got_lo12:
VK_AARCH64_LO12, // :lo12:
VK_AARCH64_ABS_G0, // :abs_g0:
VK_AARCH64_ABS_G0_NC, // :abs_g0_nc:
VK_AARCH64_ABS_G1,
VK_AARCH64_ABS_G1_NC,
VK_AARCH64_ABS_G2,
VK_AARCH64_ABS_G2_NC,
VK_AARCH64_ABS_G3,
VK_AARCH64_SABS_G0, // :abs_g0_s:
VK_AARCH64_SABS_G1,
VK_AARCH64_SABS_G2,
VK_AARCH64_DTPREL_G2, // :dtprel_g2:
VK_AARCH64_DTPREL_G1,
VK_AARCH64_DTPREL_G1_NC,
VK_AARCH64_DTPREL_G0,
VK_AARCH64_DTPREL_G0_NC,
VK_AARCH64_DTPREL_HI12,
VK_AARCH64_DTPREL_LO12,
VK_AARCH64_DTPREL_LO12_NC,
VK_AARCH64_GOTTPREL_G1, // :gottprel:
VK_AARCH64_GOTTPREL_G0_NC,
VK_AARCH64_GOTTPREL,
VK_AARCH64_GOTTPREL_LO12,
VK_AARCH64_TPREL_G2, // :tprel:
VK_AARCH64_TPREL_G1,
VK_AARCH64_TPREL_G1_NC,
VK_AARCH64_TPREL_G0,
VK_AARCH64_TPREL_G0_NC,
VK_AARCH64_TPREL_HI12,
VK_AARCH64_TPREL_LO12,
VK_AARCH64_TPREL_LO12_NC,
VK_AARCH64_TLSDESC, // :tlsdesc:
VK_AARCH64_TLSDESC_LO12
};
private:
const VariantKind Kind;
const MCExpr *Expr;
explicit AArch64MCExpr(VariantKind _Kind, const MCExpr *_Expr)
: Kind(_Kind), Expr(_Expr) {}
public:
/// @name Construction
/// @{
static const AArch64MCExpr *Create(VariantKind Kind, const MCExpr *Expr,
MCContext &Ctx);
static const AArch64MCExpr *CreateLo12(const MCExpr *Expr, MCContext &Ctx) {
return Create(VK_AARCH64_LO12, Expr, Ctx);
}
static const AArch64MCExpr *CreateGOT(const MCExpr *Expr, MCContext &Ctx) {
return Create(VK_AARCH64_GOT, Expr, Ctx);
}
static const AArch64MCExpr *CreateGOTLo12(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_GOT_LO12, Expr, Ctx);
}
static const AArch64MCExpr *CreateDTPREL_G1(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_DTPREL_G1, Expr, Ctx);
}
static const AArch64MCExpr *CreateDTPREL_G0_NC(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_DTPREL_G0_NC, Expr, Ctx);
}
static const AArch64MCExpr *CreateGOTTPREL(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_GOTTPREL, Expr, Ctx);
}
static const AArch64MCExpr *CreateGOTTPRELLo12(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_GOTTPREL_LO12, Expr, Ctx);
}
static const AArch64MCExpr *CreateTLSDesc(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_TLSDESC, Expr, Ctx);
}
static const AArch64MCExpr *CreateTLSDescLo12(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_TLSDESC_LO12, Expr, Ctx);
}
static const AArch64MCExpr *CreateTPREL_G1(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_TPREL_G1, Expr, Ctx);
}
static const AArch64MCExpr *CreateTPREL_G0_NC(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_TPREL_G0_NC, Expr, Ctx);
}
static const AArch64MCExpr *CreateABS_G3(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_ABS_G3, Expr, Ctx);
}
static const AArch64MCExpr *CreateABS_G2_NC(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_ABS_G2_NC, Expr, Ctx);
}
static const AArch64MCExpr *CreateABS_G1_NC(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_ABS_G1_NC, Expr, Ctx);
}
static const AArch64MCExpr *CreateABS_G0_NC(const MCExpr *Expr,
MCContext &Ctx) {
return Create(VK_AARCH64_ABS_G0_NC, Expr, Ctx);
}
/// @}
/// @name Accessors
/// @{
/// getOpcode - Get the kind of this expression.
VariantKind getKind() const { return Kind; }
/// getSubExpr - Get the child of this expression.
const MCExpr *getSubExpr() const { return Expr; }
/// @}
void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const override;
void AddValueSymbols(MCAssembler *) const override;
const MCSection *FindAssociatedSection() const override {
return getSubExpr()->FindAssociatedSection();
}
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;
}
static bool classof(const AArch64MCExpr *) { return true; }
};
} // end namespace llvm
#endif

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//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides AArch64 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "AArch64MCTargetDesc.h"
#include "AArch64ELFStreamer.h"
#include "AArch64MCAsmInfo.h"
#include "InstPrinter/AArch64InstPrinter.h"
#include "llvm/ADT/APInt.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
#define GET_REGINFO_MC_DESC
#include "AArch64GenRegisterInfo.inc"
#define GET_INSTRINFO_MC_DESC
#include "AArch64GenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "AArch64GenSubtargetInfo.inc"
MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT,
StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
return X;
}
static MCInstrInfo *createAArch64MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitAArch64MCInstrInfo(X);
return X;
}
static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) {
MCRegisterInfo *X = new MCRegisterInfo();
InitAArch64MCRegisterInfo(X, AArch64::X30);
return X;
}
static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
StringRef TT) {
Triple TheTriple(TT);
MCAsmInfo *MAI = new AArch64ELFMCAsmInfo(TT);
unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
MAI->addInitialFrameState(Inst);
return MAI;
}
static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC) {
// On ELF platforms the default static relocation model has a smart enough
// linker to cope with referencing external symbols defined in a shared
// library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
RM = Reloc::Static;
}
if (CM == CodeModel::Default)
CM = CodeModel::Small;
else if (CM == CodeModel::JITDefault) {
// The default MCJIT memory managers make no guarantees about where they can
// find an executable page; JITed code needs to be able to refer to globals
// no matter how far away they are.
CM = CodeModel::Large;
}
X->InitMCCodeGenInfo(RM, CM, OL);
return X;
}
static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
MCContext &Ctx, MCAsmBackend &MAB,
raw_ostream &OS,
MCCodeEmitter *Emitter,
const MCSubtargetInfo &STI,
bool RelaxAll,
bool NoExecStack) {
Triple TheTriple(TT);
return createAArch64ELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
}
static MCInstPrinter *createAArch64MCInstPrinter(const Target &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI) {
if (SyntaxVariant == 0)
return new AArch64InstPrinter(MAI, MII, MRI, STI);
return nullptr;
}
namespace {
class AArch64MCInstrAnalysis : public MCInstrAnalysis {
public:
AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
bool isUnconditionalBranch(const MCInst &Inst) const override {
if (Inst.getOpcode() == AArch64::Bcc
&& Inst.getOperand(0).getImm() == A64CC::AL)
return true;
return MCInstrAnalysis::isUnconditionalBranch(Inst);
}
bool isConditionalBranch(const MCInst &Inst) const override {
if (Inst.getOpcode() == AArch64::Bcc
&& Inst.getOperand(0).getImm() == A64CC::AL)
return false;
return MCInstrAnalysis::isConditionalBranch(Inst);
}
bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
uint64_t Size, uint64_t &Target) const override {
unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
// FIXME: We only handle PCRel branches for now.
if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
!= MCOI::OPERAND_PCREL)
return false;
int64_t Imm = Inst.getOperand(LblOperand).getImm();
Target = Addr + Imm;
return true;
}
};
}
static MCInstrAnalysis *createAArch64MCInstrAnalysis(const MCInstrInfo *Info) {
return new AArch64MCInstrAnalysis(Info);
}
extern "C" void LLVMInitializeAArch64TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn A(TheAArch64leTarget, createAArch64MCAsmInfo);
RegisterMCAsmInfoFn B(TheAArch64beTarget, createAArch64MCAsmInfo);
// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
createAArch64MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
createAArch64MCCodeGenInfo);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget,
createAArch64MCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget,
createAArch64MCInstrInfo);
// Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget,
createAArch64MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget,
createAArch64MCRegisterInfo);
// Register the MC subtarget info.
using AArch64_MC::createAArch64MCSubtargetInfo;
TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
createAArch64MCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
createAArch64MCSubtargetInfo);
// Register the MC instruction analyzer.
TargetRegistry::RegisterMCInstrAnalysis(TheAArch64leTarget,
createAArch64MCInstrAnalysis);
TargetRegistry::RegisterMCInstrAnalysis(TheAArch64beTarget,
createAArch64MCInstrAnalysis);
// Register the MC Code Emitter
TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
createAArch64MCCodeEmitter);
TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
createAArch64MCCodeEmitter);
// Register the asm backend.
TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget,
createAArch64leAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
createAArch64beAsmBackend);
// Register the object streamer.
TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget,
createMCStreamer);
TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget,
createMCStreamer);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
createAArch64MCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
createAArch64MCInstPrinter);
}

72
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
View File

@ -1,72 +0,0 @@
//===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides AArch64 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64MCTARGETDESC_H
#define LLVM_AARCH64MCTARGETDESC_H
#include "llvm/Support/DataTypes.h"
namespace llvm {
class MCAsmBackend;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class StringRef;
class Target;
class raw_ostream;
extern Target TheAArch64leTarget;
extern Target TheAArch64beTarget;
namespace AArch64_MC {
MCSubtargetInfo *createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS);
}
MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx);
MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS,
uint8_t OSABI,
bool IsLittleEndian);
MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU);
MCAsmBackend *createAArch64beAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU);
} // End llvm namespace
// Defines symbolic names for AArch64 registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "AArch64GenRegisterInfo.inc"
// Defines symbolic names for the AArch64 instructions.
//
#define GET_INSTRINFO_ENUM
#include "AArch64GenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "AArch64GenSubtargetInfo.inc"
#endif

9
lib/Target/AArch64/MCTargetDesc/CMakeLists.txt
View File

@ -1,9 +0,0 @@
add_llvm_library(LLVMAArch64Desc
AArch64AsmBackend.cpp
AArch64ELFObjectWriter.cpp
AArch64ELFStreamer.cpp
AArch64MCAsmInfo.cpp
AArch64MCCodeEmitter.cpp
AArch64MCExpr.cpp
AArch64MCTargetDesc.cpp
)

24
lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt
View File

@ -1,24 +0,0 @@
;===- ./lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt ----------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = AArch64Desc
parent = AArch64
required_libraries = AArch64AsmPrinter AArch64Info MC Support
add_to_library_groups = AArch64

16
lib/Target/AArch64/MCTargetDesc/Makefile
View File

@ -1,16 +0,0 @@
##===- lib/Target/AArch64/TargetDesc/Makefile --------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAArch64Desc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

30
lib/Target/AArch64/Makefile
View File

@ -1,30 +0,0 @@
##===- lib/Target/AArch64/Makefile -------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = LLVMAArch64CodeGen
TARGET = AArch64
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = AArch64GenAsmMatcher.inc \
AArch64GenAsmWriter.inc \
AArch64GenCallingConv.inc \
AArch64GenDAGISel.inc \
AArch64GenDisassemblerTables.inc \
AArch64GenInstrInfo.inc \
AArch64GenMCCodeEmitter.inc \
AArch64GenMCPseudoLowering.inc \
AArch64GenRegisterInfo.inc \
AArch64GenSubtargetInfo.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc Utils
include $(LEVEL)/Makefile.common

2
lib/Target/AArch64/README.txt
View File

@ -1,2 +0,0 @@
This file will contain changes that need to be made before AArch64 can become an
officially supported target. Currently a placeholder.

27
lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
View File

@ -1,27 +0,0 @@
//===-- AArch64TargetInfo.cpp - AArch64 Target Implementation -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the key registration step for the architecture.
//
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
Target llvm::TheAArch64leTarget;
Target llvm::TheAArch64beTarget;
extern "C" void LLVMInitializeAArch64TargetInfo() {
RegisterTarget<Triple::aarch64, /*HasJIT=*/true>
X(TheAArch64leTarget, "aarch64", "AArch64 (ARM 64-bit little endian target)");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true>
Y(TheAArch64beTarget, "aarch64_be", "AArch64 (ARM 64-bit big endian target)");
}

3
lib/Target/AArch64/TargetInfo/CMakeLists.txt
View File

@ -1,3 +0,0 @@
add_llvm_library(LLVMAArch64Info
AArch64TargetInfo.cpp
)

23
lib/Target/AArch64/TargetInfo/LLVMBuild.txt
View File

@ -1,23 +0,0 @@
;===- ./lib/Target/AArch64/TargetInfo/LLVMBuild.txt ------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = AArch64Info
parent = AArch64
required_libraries = Support
add_to_library_groups = AArch64

15
lib/Target/AArch64/TargetInfo/Makefile
View File

@ -1,15 +0,0 @@
##===- lib/Target/AArch64/TargetInfo/Makefile --------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAArch64Info
# Hack: we need to include 'main' target directory to grab private headers
CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

1173
lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
View File

File diff suppressed because it is too large Load Diff

1138
lib/Target/AArch64/Utils/AArch64BaseInfo.h
View File

File diff suppressed because it is too large Load Diff

3
lib/Target/AArch64/Utils/CMakeLists.txt
View File

@ -1,3 +0,0 @@
add_llvm_library(LLVMAArch64Utils
AArch64BaseInfo.cpp
)

23
lib/Target/AArch64/Utils/LLVMBuild.txt
View File

@ -1,23 +0,0 @@
;===- ./lib/Target/AArch646/Utils/LLVMBuild.txt ----------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;
[component_0]
type = Library
name = AArch64Utils
parent = AArch64
required_libraries = Support
add_to_library_groups = AArch64

15
lib/Target/AArch64/Utils/Makefile
View File

@ -1,15 +0,0 @@
##===- lib/Target/AArch64/Utils/Makefile -------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAArch64Utils
# Hack: we need to include 'main' AArch64 target directory to grab private headers
#CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

3
lib/Target/ARM64/ARM64AsmPrinter.cpp
View File

@ -508,4 +508,7 @@ void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
extern "C" void LLVMInitializeARM64AsmPrinter() {
RegisterAsmPrinter<ARM64AsmPrinter> X(TheARM64leTarget);
RegisterAsmPrinter<ARM64AsmPrinter> Y(TheARM64beTarget);
RegisterAsmPrinter<ARM64AsmPrinter> Z(TheAArch64leTarget);
RegisterAsmPrinter<ARM64AsmPrinter> W(TheAArch64beTarget);
}

3
lib/Target/ARM64/ARM64TargetMachine.cpp
View File

@ -57,6 +57,9 @@ extern "C" void LLVMInitializeARM64Target() {
// Register the target.
RegisterTargetMachine<ARM64leTargetMachine> X(TheARM64leTarget);
RegisterTargetMachine<ARM64beTargetMachine> Y(TheARM64beTarget);
RegisterTargetMachine<ARM64leTargetMachine> Z(TheAArch64leTarget);
RegisterTargetMachine<ARM64beTargetMachine> W(TheAArch64beTarget);
}
/// TargetMachine ctor - Create an ARM64 architecture model.

3
lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
View File

@ -3957,6 +3957,9 @@ ARM64AsmParser::classifySymbolRef(const MCExpr *Expr,
extern "C" void LLVMInitializeARM64AsmParser() {
RegisterMCAsmParser<ARM64AsmParser> X(TheARM64leTarget);
RegisterMCAsmParser<ARM64AsmParser> Y(TheARM64beTarget);
RegisterMCAsmParser<ARM64AsmParser> Z(TheAArch64leTarget);
RegisterMCAsmParser<ARM64AsmParser> W(TheAArch64beTarget);
}
#define GET_REGISTER_MATCHER

9
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
View File

@ -242,6 +242,15 @@ extern "C" void LLVMInitializeARM64Disassembler() {
createARM64ExternalSymbolizer);
TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget,
createARM64ExternalSymbolizer);
TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
createARM64Disassembler);
TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
createARM64Disassembler);
TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
createARM64ExternalSymbolizer);
TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
createARM64ExternalSymbolizer);
}
static const unsigned FPR128DecoderTable[] = {

26
lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
View File

@ -141,44 +141,70 @@ extern "C" void LLVMInitializeARM64TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(TheARM64leTarget, createARM64MCAsmInfo);
RegisterMCAsmInfoFn Y(TheARM64beTarget, createARM64MCAsmInfo);
RegisterMCAsmInfoFn Z(TheAArch64leTarget, createARM64MCAsmInfo);
RegisterMCAsmInfoFn W(TheAArch64beTarget, createARM64MCAsmInfo);
// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheARM64leTarget,
createARM64MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheARM64beTarget,
createARM64MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
createARM64MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
createARM64MCCodeGenInfo);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheARM64leTarget, createARM64MCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheARM64beTarget, createARM64MCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget, createARM64MCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget, createARM64MCInstrInfo);
// Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheARM64leTarget, createARM64MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheARM64beTarget, createARM64MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget, createARM64MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget, createARM64MCRegisterInfo);
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheARM64leTarget,
createARM64MCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheARM64beTarget,
createARM64MCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
createARM64MCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
createARM64MCSubtargetInfo);
// Register the asm backend.
TargetRegistry::RegisterMCAsmBackend(TheARM64leTarget, createARM64leAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheARM64beTarget, createARM64beAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget, createARM64leAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget, createARM64beAsmBackend);
// Register the MC Code Emitter
TargetRegistry::RegisterMCCodeEmitter(TheARM64leTarget,
createARM64MCCodeEmitter);
TargetRegistry::RegisterMCCodeEmitter(TheARM64beTarget,
createARM64MCCodeEmitter);
TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
createARM64MCCodeEmitter);
TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
createARM64MCCodeEmitter);
// Register the object streamer.
TargetRegistry::RegisterMCObjectStreamer(TheARM64leTarget, createMCStreamer);
TargetRegistry::RegisterMCObjectStreamer(TheARM64beTarget, createMCStreamer);
TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget, createMCStreamer);
TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget, createMCStreamer);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheARM64leTarget,
createARM64MCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheARM64beTarget,
createARM64MCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
createARM64MCInstPrinter);
TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
createARM64MCInstPrinter);
}

2
lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h
View File

@ -31,6 +31,8 @@ class raw_ostream;
extern Target TheARM64leTarget;
extern Target TheARM64beTarget;
extern Target TheAArch64leTarget;
extern Target TheAArch64beTarget;
MCCodeEmitter *createARM64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,

7
lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp
View File

@ -14,6 +14,8 @@ using namespace llvm;
namespace llvm {
Target TheARM64leTarget;
Target TheARM64beTarget;
Target TheAArch64leTarget;
Target TheAArch64beTarget;
} // end namespace llvm
extern "C" void LLVMInitializeARM64TargetInfo() {
@ -21,4 +23,9 @@ extern "C" void LLVMInitializeARM64TargetInfo() {
"ARM64 (little endian)");
RegisterTarget<Triple::arm64_be, /*HasJIT=*/true> Y(TheARM64beTarget, "arm64_be",
"ARM64 (big endian)");
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
TheAArch64leTarget, "aarch64", "ARM64 (little endian)");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
TheAArch64beTarget, "aarch64_be", "ARM64 (big endian)");
}

2
lib/Target/LLVMBuild.txt
View File

@ -16,7 +16,7 @@
;===------------------------------------------------------------------------===;
[common]
subdirectories = AArch64 ARM ARM64 CppBackend Hexagon MSP430 NVPTX Mips PowerPC R600 Sparc SystemZ X86 XCore
subdirectories = ARM ARM64 CppBackend Hexagon MSP430 NVPTX Mips PowerPC R600 Sparc SystemZ X86 XCore
; This is a special group whose required libraries are extended (by llvm-build)
; with the best execution engine (the native JIT, if available, or the

7
test/CodeGen/AArch64/128bit_load_store.ll
View File

@ -1,4 +1,3 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
define void @test_store_f128(fp128* %ptr, fp128 %val) #0 {
@ -21,9 +20,6 @@ define void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
; CHECK-ARM64-LABEL: test_vstrq_p128
; CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-AARCH64-LABEL: test_vstrq_p128
; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}]
entry:
%0 = bitcast i128* %ptr to fp128*
%1 = bitcast i128 %val to fp128
@ -35,9 +31,6 @@ define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
; CHECK-ARM64-LABEL: test_vldrq_p128
; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-AARCH64-LABEL: test_vldrq_p128
; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
entry:
%0 = bitcast i128* %ptr to fp128*
%1 = load fp128* %0, align 16

2
test/CodeGen/AArch64/adc.ll
View File

@ -1,5 +1,3 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=arm64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s

1
test/CodeGen/AArch64/addsub-shifted.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
@var32 = global i32 0

1
test/CodeGen/AArch64/addsub.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-linux-gnu | FileCheck %s
; Note that this should be refactored (for efficiency if nothing else)

1
test/CodeGen/AArch64/addsub_ext.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-linux-gnu | FileCheck %s
@var8 = global i8 0

21
test/CodeGen/AArch64/alloca.ll
View File

@ -1,6 +1,4 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-AARCH64 %s
; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s
declare void @use_addr(i8*)
@ -54,8 +52,6 @@ define i64 @test_alloca_with_local(i64 %n) {
; CHECK: bl use_addr
%val = load i64* %loc
; CHECK-AARCH64: sub x[[TMP:[0-9]+]], x29, #[[LOC_FROM_FP]]
; CHECK-AARCH64: ldr x0, [x[[TMP]]]
; CHECK-ARM64: ldur x0, [x29, #-[[LOC_FROM_FP]]]
@ -68,13 +64,7 @@ define i64 @test_alloca_with_local(i64 %n) {
define void @test_variadic_alloca(i64 %n, ...) {
; CHECK-LABEL: test_variadic_alloca:
; CHECK-AARCH64: sub sp, sp, #{{[0-9]+}}
; CHECK-AARCH64: add x29, sp, #192
; CHECK-AARCH64: sub [[TMP:x[0-9]+]], x29, #192
; CHECK-AARCH64: add x8, [[TMP]], #0
; CHECK-AARCH64-FP: str q7, [x8, #112]
; [...]
; CHECK-AARCH64-FP: str q1, [x8, #16]
; CHECK-NOFP-AARCH64: sub sp, sp, #80
@ -112,9 +102,6 @@ define void @test_variadic_alloca(i64 %n, ...) {
; CHECK: bl use_addr
ret void
; CHECK-AARCH64: sub sp, x29, #192
; CHECK-AARCH64: ldp x29, x30, [sp, #192]
; CHECK-AARCH64: add sp, sp, #208
; CHECK-NOFP-AARCH64: sub sp, x29, #64
; CHECK-NOFP-AARCH64: ldp x29, x30, [sp, #64]
@ -127,11 +114,6 @@ define void @test_variadic_alloca(i64 %n, ...) {
define void @test_alloca_large_frame(i64 %n) {
; CHECK-LABEL: test_alloca_large_frame:
; CHECK-AARCH64: sub sp, sp, #496
; CHECK-AARCH64: stp x29, x30, [sp, #480]
; CHECK-AARCH64: add x29, sp, #480
; CHECK-AARCH64: sub sp, sp, #48
; CHECK-AARCH64: sub sp, sp, #1953, lsl #12
; CHECK-ARM64: stp x20, x19, [sp, #-32]!
; CHECK-ARM64: stp x29, x30, [sp, #16]
@ -145,9 +127,6 @@ define void @test_alloca_large_frame(i64 %n) {
call void @use_addr_loc(i8* %addr1, i64* %addr2)
ret void
; CHECK-AARCH64: sub sp, x29, #480
; CHECK-AARCH64: ldp x29, x30, [sp, #480]
; CHECK-AARCH64: add sp, sp, #496
; CHECK-ARM64: sub sp, x29, #16
; CHECK-ARM64: ldp x29, x30, [sp, #16]

1
test/CodeGen/AArch64/analyze-branch.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; RUN: llc -mtriple=arm64-none-linux-gnu < %s | FileCheck %s
; This test checks that LLVM can do basic stripping and reapplying of branches

74
test/CodeGen/AArch64/andCmpBrToTBZ.ll
View File

@ -1,74 +0,0 @@
; RUN: llc -O1 -march=aarch64 -enable-andcmp-sinking=true < %s | FileCheck %s
; arm64 has separate copy of this test
; ModuleID = 'and-cbz-extr-mr.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "aarch64-none-linux-gnu"
define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 {
; CHECK: foo:
entry:
%tobool = icmp eq i8* %str14, null
br i1 %tobool, label %return, label %if.end
; CHECK: %if.end
; CHECK: tbz
if.end: ; preds = %entry
%and.i.i.i = and i32 %int1, 4
%tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
land.rhs.i: ; preds = %if.end
%cmp.i.i.i = icmp eq i8* %str12, %str13
br i1 %cmp.i.i.i, label %if.then3, label %lor.rhs.i.i.i
lor.rhs.i.i.i: ; preds = %land.rhs.i
%cmp.i13.i.i.i = icmp eq i8* %str10, %str11
br i1 %cmp.i13.i.i.i, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, label %if.end5
_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds = %lor.rhs.i.i.i
%cmp.i.i.i.i = icmp eq i8* %str8, %str9
br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
if.then3: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
%tmp11 = load i8* %str14, align 8
%tmp12 = and i8 %tmp11, 2
%tmp13 = icmp ne i8 %tmp12, 0
br label %return
if.end5: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
; CHECK: %if.end5
; CHECK: tbz
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
land.rhs.i19: ; preds = %if.end5
%cmp.i.i.i18 = icmp eq i8* %str6, %str7
br i1 %cmp.i.i.i18, label %if.then7, label %lor.rhs.i.i.i23
lor.rhs.i.i.i23: ; preds = %land.rhs.i19
%cmp.i13.i.i.i22 = icmp eq i8* %str3, %str4
br i1 %cmp.i13.i.i.i22, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, label %if.end12
_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28: ; preds = %lor.rhs.i.i.i23
%cmp.i.i.i.i26 = icmp eq i8* %str1, %str2
br i1 %cmp.i.i.i.i26, label %if.then7, label %if.end12
if.then7: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %land.rhs.i19
br i1 %isTextField, label %if.then9, label %if.end12
if.then9: ; preds = %if.then7
%tmp23 = load i8* %str5, align 8
%tmp24 = and i8 %tmp23, 2
%tmp25 = icmp ne i8 %tmp24, 0
br label %return
if.end12: ; preds = %if.then7, %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %lor.rhs.i.i.i23, %if.end5, %if.end
%lnot = xor i1 %IsEditable, true
br label %return
return: ; preds = %if.end12, %if.then9, %if.then3, %entry
%retval.0 = phi i1 [ %tmp13, %if.then3 ], [ %tmp25, %if.then9 ], [ %lnot, %if.end12 ], [ true, %entry ]
ret i1 %retval.0
}
attributes #0 = { nounwind ssp }

1
test/CodeGen/AArch64/assertion-rc-mismatch.ll
View File

@ -1,4 +1,3 @@
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
; Test case related to <rdar://problem/15633429>.

1
test/CodeGen/AArch64/atomic-ops-not-barriers.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
define i32 @foo(i32* %var, i1 %cond) {

34
test/CodeGen/AArch64/atomic-ops.ll
View File

@ -1,5 +1,3 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-REG %s
; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
@ -502,8 +500,6 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxtb
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
; CHECK-ARM64-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxtb
@ -528,8 +524,6 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxth
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
; CHECK-ARM64-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]]
; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxth
@ -555,8 +549,6 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
@ -581,8 +573,6 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
; x0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, le
@ -607,8 +597,6 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxtb
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
; CHECK-ARM64-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxtb
@ -634,8 +622,6 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxth
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
; CHECK-ARM64-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]]
; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxth
@ -661,8 +647,6 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
@ -687,8 +671,6 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
; x0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt
; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
@ -713,8 +695,6 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxtb
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxtb
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
@ -739,8 +719,6 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxth
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxth
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
@ -765,8 +743,6 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
@ -791,8 +767,6 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
; x0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, ls
@ -817,8 +791,6 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxtb
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxtb
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
@ -843,8 +815,6 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxth
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxth
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
@ -869,8 +839,6 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
; w0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
@ -895,8 +863,6 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
; x0 below is a reasonable guess but could change: it certainly comes into the
; function there.
; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo
; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi

1
test/CodeGen/AArch64/basic-pic.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic %s -o - | FileCheck %s
; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -relocation-model=pic %s -o - | FileCheck %s
@var = global i32 0

1
test/CodeGen/AArch64/bitfield-insert-0.ll
View File

@ -1,4 +1,3 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -disassemble - | FileCheck %s
; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj -o - %s | llvm-objdump -disassemble - | FileCheck %s
; The encoding of lsb -> immr in the CGed bitfield instructions was wrong at one

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