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Fix typo: should have been testing that X was odd, not V.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124533 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -715,16 +715,16 @@ bool llvm::isKnownNonZero(Value *V, const TargetData *TD, unsigned Depth) {
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if (isa<SExtInst>(V) || isa<ZExtInst>(V))
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return isKnownNonZero(cast<Instruction>(V)->getOperand(0), TD, Depth);
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// shl X, A != 0 if X is odd. Note that the value of the shift is undefined
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// shl X, Y != 0 if X is odd. Note that the value of the shift is undefined
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// if the lowest bit is shifted off the end.
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if (BitWidth && match(V, m_Shl(m_Value(X), m_Value(Y)))) {
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APInt KnownZero(BitWidth, 0);
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APInt KnownOne(BitWidth, 0);
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ComputeMaskedBits(V, APInt(BitWidth, 1), KnownZero, KnownOne, TD, Depth);
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ComputeMaskedBits(X, APInt(BitWidth, 1), KnownZero, KnownOne, TD, Depth);
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if (KnownOne[0])
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return true;
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}
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// shr X, A != 0 if X is negative. Note that the value of the shift is not
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// shr X, Y != 0 if X is negative. Note that the value of the shift is not
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// defined if the sign bit is shifted off the end.
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else if (match(V, m_Shr(m_Value(X), m_Value(Y)))) {
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bool XKnownNonNegative, XKnownNegative;
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@ -108,3 +108,27 @@ define i1 @or(i32 %x) {
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ret i1 %c
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; CHECK: ret i1 false
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}
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define i1 @shl(i32 %x) {
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; CHECK: @shl
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%s = shl i32 1, %x
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%c = icmp eq i32 %s, 0
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ret i1 %c
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; CHECK: ret i1 false
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}
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define i1 @lshr(i32 %x) {
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; CHECK: @lshr
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%s = lshr i32 -1, %x
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%c = icmp eq i32 %s, 0
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ret i1 %c
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; CHECK: ret i1 false
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}
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define i1 @ashr(i32 %x) {
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; CHECK: @ashr
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%s = ashr i32 -1, %x
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%c = icmp eq i32 %s, 0
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ret i1 %c
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; CHECK: ret i1 false
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}
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