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Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139067 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4780,17 +4780,33 @@ defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
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int_x86_ssse3_pmul_hr_sw_128>;
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}
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
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let Predicates = [HasSSSE3] in {
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(PSHUFBrr128 VR128:$src, VR128:$mask)>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>;
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def : Pat<(X86psignb VR128:$src1, VR128:$src2),
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(PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
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def : Pat<(X86psignw VR128:$src1, VR128:$src2),
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(PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
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def : Pat<(X86psignd VR128:$src1, VR128:$src2),
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(PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
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def : Pat<(X86psignb VR128:$src1, VR128:$src2),
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(PSIGNBrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(X86psignw VR128:$src1, VR128:$src2),
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(PSIGNWrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(X86psignd VR128:$src1, VR128:$src2),
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(PSIGNDrr128 VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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(VPSHUFBrr128 VR128:$src, VR128:$mask)>;
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(VPSHUFBrm128 VR128:$src, addr:$mask)>;
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def : Pat<(X86psignb VR128:$src1, VR128:$src2),
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(VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(X86psignw VR128:$src1, VR128:$src2),
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(VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(X86psignd VR128:$src1, VR128:$src2),
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(VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
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}
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Align Instruction Patterns
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