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Add AT to the list of registers clobbered by branches so that it is available

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as a scratch register when they are expanded to long branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158432 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-06-14 01:17:59 +00:00
parent c56a7bb051
commit 91625aab60
1 changed files with 4 additions and 0 deletions
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4
lib/Target/Mips/MipsInstrInfo.td
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@ -561,6 +561,7 @@ class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
let Defs = [AT];
}
class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
@ -572,6 +573,7 @@ class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
let Defs = [AT];
}
// SetCC
@ -601,6 +603,7 @@ class JumpFJ<bits<6> op, string instr_asm>:
let hasDelaySlot = 1;
let Predicates = [RelocStatic, HasStandardEncoding];
let DecoderMethod = "DecodeJumpTarget";
let Defs = [AT];
}
// Unconditional branch
@ -614,6 +617,7 @@ class UncondBranch<bits<6> op, string instr_asm>:
let isBarrier = 1;
let hasDelaySlot = 1;
let Predicates = [RelocPIC, HasStandardEncoding];
let Defs = [AT];
}
let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,