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Stripped trailing whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239672 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6356,7 +6356,7 @@ static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
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///
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/// This helper function produces an 8-bit shuffle immediate corresponding to
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/// the ubiquitous shuffle encoding scheme used in x86 instructions for
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/// shuffling 8 lanes.
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/// shuffling 8 lanes.
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static SDValue get1bitLaneShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
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SelectionDAG &DAG) {
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assert(Mask.size() <= 8 &&
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@ -13021,11 +13021,11 @@ SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
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RecipOp = "vec-sqrtf";
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else
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return SDValue();
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TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
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if (!Recips.isEnabled(RecipOp))
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return SDValue();
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RefinementSteps = Recips.getRefinementSteps(RecipOp);
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UseOneConstNR = false;
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return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
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@ -13038,7 +13038,7 @@ SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
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unsigned &RefinementSteps) const {
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EVT VT = Op.getValueType();
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const char *RecipOp;
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// SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
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// TODO: Add support for AVX512 (v16f32).
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// It is likely not profitable to do this for f64 because a double-precision
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@ -13053,7 +13053,7 @@ SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
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RecipOp = "vec-divf";
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else
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return SDValue();
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TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
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if (!Recips.isEnabled(RecipOp))
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return SDValue();
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@ -15110,7 +15110,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
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unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
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if (IntrWithRoundingModeOpcode != 0) {
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unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
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if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
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if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
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return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, Op.getValueType(), Src, RoundingMode),
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Mask, PassThru, Subtarget, DAG);
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