diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h
index 36b6860cf6a..36536a14ee8 100644
--- a/include/llvm/CodeGen/LiveVariables.h
+++ b/include/llvm/CodeGen/LiveVariables.h
@@ -229,7 +229,7 @@ public:
     bool Removed = false;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
+      if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
         MO.unsetIsKill();
         Removed = true;
         break;
@@ -266,7 +266,7 @@ public:
     bool Removed = false;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
+      if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
         MO.unsetIsDead();
         Removed = true;
         break;
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 4ba436b1fd9..3dbda8dc787 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -131,10 +131,6 @@ public:
 
   /// Accessors that tell you what kind of MachineOperand you're looking at.
   ///
-  bool isReg() const { return opType == MO_Register; }
-  bool isImm() const { return opType == MO_Immediate; }
-  bool isMBB() const { return opType == MO_MachineBasicBlock; }
-  
   bool isRegister() const { return opType == MO_Register; }
   bool isImmediate() const { return opType == MO_Immediate; }
   bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
@@ -145,12 +141,12 @@ public:
   bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
 
   int64_t getImm() const {
-    assert(isImm() && "Wrong MachineOperand accessor");
+    assert(isImmediate() && "Wrong MachineOperand accessor");
     return contents.immedVal;
   }
   
   int64_t getImmedValue() const {
-    assert(isImm() && "Wrong MachineOperand accessor");
+    assert(isImmediate() && "Wrong MachineOperand accessor");
     return contents.immedVal;
   }
   MachineBasicBlock *getMBB() const {
@@ -257,11 +253,11 @@ public:
   }
 
   void setImmedValue(int64_t immVal) {
-    assert(isImm() && "Wrong MachineOperand mutator");
+    assert(isImmediate() && "Wrong MachineOperand mutator");
     contents.immedVal = immVal;
   }
   void setImm(int64_t immVal) {
-    assert(isImm() && "Wrong MachineOperand mutator");
+    assert(isImmediate() && "Wrong MachineOperand mutator");
     contents.immedVal = immVal;
   }
 
diff --git a/lib/CodeGen/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter.cpp
index b55310661e6..3d8dd75a161 100644
--- a/lib/CodeGen/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter.cpp
@@ -982,7 +982,7 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
   
   // Count the number of register definitions.
   unsigned NumDefs = 0;
-  for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
+  for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef();
        ++NumDefs)
     assert(NumDefs != NumOperands-1 && "No asm string?");
   
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 3d324b7bfc6..e7abd47f536 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -413,7 +413,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, unsigned reg) {
           bool HasUse = mop.isUse();
           bool HasDef = mop.isDef();
           for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
-            if (MI->getOperand(j).isReg() &&
+            if (MI->getOperand(j).isRegister() &&
                 MI->getOperand(j).getReg() == li.reg) {
               MI->getOperand(j).setReg(NewVReg);
               HasUse |= MI->getOperand(j).isUse();
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index dd5afcc432b..57396b74168 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -78,7 +78,7 @@ LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isKill()) {
+    if (MO.isRegister() && MO.isKill()) {
       if ((MO.getReg() == Reg) ||
           (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            MRegisterInfo::isPhysicalRegister(Reg) &&
@@ -92,7 +92,7 @@ bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDead()) {
+    if (MO.isRegister() && MO.isDead()) {
       if ((MO.getReg() == Reg) ||
           (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            MRegisterInfo::isPhysicalRegister(Reg) &&
@@ -106,7 +106,7 @@ bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
       return true;
   }
   return false;
@@ -190,7 +190,7 @@ bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
   bool Found = false;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isUse()) {
+    if (MO.isRegister() && MO.isUse()) {
       unsigned Reg = MO.getReg();
       if (!Reg)
         continue;
@@ -221,7 +221,7 @@ bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
   bool Found = false;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDef()) {
+    if (MO.isRegister() && MO.isDef()) {
       unsigned Reg = MO.getReg();
       if (!Reg)
         continue;
@@ -614,7 +614,7 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI,
 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isKill()) {
+    if (MO.isRegister() && MO.isKill()) {
       MO.unsetIsKill();
       unsigned Reg = MO.getReg();
       if (MRegisterInfo::isVirtualRegister(Reg)) {
@@ -630,7 +630,7 @@ void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDead()) {
+    if (MO.isRegister() && MO.isDead()) {
       MO.unsetIsDead();
       unsigned Reg = MO.getReg();
       if (MRegisterInfo::isVirtualRegister(Reg)) {
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index dbf7968a744..7acd03e1ccb 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -66,7 +66,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
    
    assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
           MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
-          MI->getOperand(2).isImm() && "Malformed extract_subreg");
+          MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
 
    unsigned SuperReg = MI->getOperand(1).getReg();
    unsigned SubIdx = MI->getOperand(2).getImm();
@@ -113,7 +113,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
   if (MI->getNumOperands() == 3) {
     assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
            (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
-            MI->getOperand(2).isImm() && "Invalid extract_subreg");
+            MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
     DstReg = MI->getOperand(0).getReg();
     SrcReg = DstReg;
     InsReg = MI->getOperand(1).getReg();
@@ -122,7 +122,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
            (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
            (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
-            MI->getOperand(3).isImm() && "Invalid extract_subreg");
+            MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
     DstReg = MI->getOperand(0).getReg();
     SrcReg = MI->getOperand(1).getReg();
     InsReg = MI->getOperand(2).getReg();
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index d6aab291f90..1634c7880e2 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -188,7 +188,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = getOperand(i);
-    if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
+    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
       if (!isKill || MO.isKill())
         return i;
   }
@@ -200,7 +200,7 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     MachineOperand &MO = getOperand(i);
-    if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
+    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
       return &MO;
   }
   return NULL;
@@ -225,7 +225,7 @@ int MachineInstr::findFirstPredOperandIdx() const {
 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
+    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
       continue;
     for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
       MachineOperand &MOp = getOperand(j);
@@ -248,7 +248,7 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) {
       if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
         const MachineOperand &MO = MI->getOperand(i);
         // Predicated operands must be last operands.
-        if (MO.isReg())
+        if (MO.isRegister())
           addRegOperand(MO.getReg(), false);
         else {
           addImmOperand(MO.getImm());
@@ -319,7 +319,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
   unsigned StartOp = 0;
 
    // Specialize printing if op#0 is definition
-  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
+  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
     ::print(getOperand(0), OS, TM);
     if (getOperand(0).isDead())
       OS << "<dead>";
@@ -337,7 +337,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
     OS << " ";
     ::print(mop, OS, TM);
 
-    if (mop.isReg()) {
+    if (mop.isRegister()) {
       if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
         OS << "<";
         bool NeedComma = false;
@@ -381,7 +381,7 @@ void MachineInstr::print(std::ostream &os) const {
 
   for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
     os << "\t" << getOperand(i);
-    if (getOperand(i).isReg() && getOperand(i).isDef())
+    if (getOperand(i).isRegister() && getOperand(i).isDef())
       os << "<d>";
   }
 
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index ae40e58d032..15592128480 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -102,7 +102,7 @@ void RegScavenger::forward() {
   BitVector ChangedRegs(NumPhysRegs);
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isUse())
+    if (!MO.isRegister() || !MO.isUse())
       continue;
     unsigned Reg = MO.getReg();
     if (Reg == 0)
@@ -125,7 +125,7 @@ void RegScavenger::forward() {
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isRegister() || !MO.isDef())
       continue;
     unsigned Reg = MO.getReg();
     // If it's dead upon def, then it is now free.
@@ -155,7 +155,7 @@ void RegScavenger::backward() {
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isRegister() || !MO.isDef())
       continue;
     // Skip two-address destination operand.
     if (TID->findTiedToSrcOperand(i) != -1)
@@ -170,7 +170,7 @@ void RegScavenger::backward() {
   BitVector ChangedRegs(NumPhysRegs);
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (!MO.isReg() || !MO.isUse())
+    if (!MO.isRegister() || !MO.isUse())
       continue;
     unsigned Reg = MO.getReg();
     if (Reg == 0)
@@ -257,7 +257,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
   // Exclude all the registers being used by the instruction.
   for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = I->getOperand(i);
-    if (MO.isReg())
+    if (MO.isRegister())
       Candidates.reset(MO.getReg());
   }
 
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 779c36a2127..5ef838c33a0 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -986,7 +986,7 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned
 
     for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
       MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && MO.isUse() && MO.getReg() &&
+      if (MO.isRegister() && MO.isUse() && MO.getReg() &&
           mri_->regsOverlap(rep(MO.getReg()), Reg)) {
         MOU = &MO;
         return MI;
@@ -1005,7 +1005,7 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned
 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDef() &&
+    if (MO.isRegister() && MO.isDef() &&
         mri_->regsOverlap(rep(MO.getReg()), Reg))
       return &MO;
   }
@@ -1017,7 +1017,7 @@ MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsig
 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isKill() && MO.getReg() &&
+    if (MO.isRegister() && MO.isKill() && MO.getReg() &&
         mri_->regsOverlap(rep(MO.getReg()), Reg))
       MO.unsetIsKill();
   }
@@ -1041,7 +1041,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
 
     for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
       MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && MO.isKill() && MO.getReg() &&
+      if (MO.isRegister() && MO.isKill() && MO.getReg() &&
           mri_->regsOverlap(rep(MO.getReg()), Reg)) {
         MO.unsetIsKill();
       }
@@ -1056,7 +1056,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDef() &&
+    if (MO.isRegister() && MO.isDef() &&
         mri_->regsOverlap(rep(MO.getReg()), Reg))
       return true;
   }
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 307a8e29612..8a1432ec897 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -446,7 +446,7 @@ static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
                             SmallVector<unsigned, 1> *KillRegs = NULL) {
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
+    if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
       continue;
     unsigned Reg = MO.getReg();
     if (KillRegs)
@@ -471,7 +471,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I,
   MachineOperand *DefOp = NULL;
   for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = DefMI->getOperand(i);
-    if (MO.isReg() && MO.isDef()) {
+    if (MO.isRegister() && MO.isDef()) {
       if (MO.getReg() == Reg)
         DefOp = &MO;
       else if (!MO.isDead())
@@ -488,7 +488,7 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I,
     MachineInstr *NMI = I;
     for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
       MachineOperand &MO = NMI->getOperand(j);
-      if (!MO.isReg() || MO.getReg() != Reg)
+      if (!MO.isRegister() || MO.getReg() != Reg)
         continue;
       if (MO.isUse())
         FoundUse = true;
@@ -511,7 +511,7 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
   const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.isUse())
+    if (!MO.isRegister() || !MO.isUse())
       continue;
     unsigned Reg = MO.getReg();
     if (Reg == 0)
@@ -535,7 +535,7 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
 
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.isDef())
+    if (!MO.isRegister() || !MO.isDef())
       continue;
     unsigned Reg = MO.getReg();
     RegKills.reset(Reg);
@@ -826,7 +826,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         bool CanReuse = true;
         int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
         if (ti != -1 &&
-            MI.getOperand(ti).isReg() && 
+            MI.getOperand(ti).isRegister() && 
             MI.getOperand(ti).getReg() == VirtReg) {
           // Okay, we have a two address operand.  We can reuse this physreg as
           // long as we are allowed to clobber the value and there isn't an
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 0ec3b9f72b0..0be0fd69b49 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -68,7 +68,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
   default: break;
   case ARM::LDR:
     if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isReg() &&
+        MI->getOperand(2).isRegister() &&
         MI->getOperand(3).isImmediate() && 
         MI->getOperand(2).getReg() == 0 &&
         MI->getOperand(3).getImmedValue() == 0) {
@@ -102,7 +102,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
   default: break;
   case ARM::STR:
     if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isReg() &&
+        MI->getOperand(2).isRegister() &&
         MI->getOperand(3).isImmediate() && 
         MI->getOperand(2).getReg() == 0 &&
         MI->getOperand(3).getImmedValue() == 0) {
@@ -521,7 +521,7 @@ bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
   bool Found = false;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
+    if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
       Pred.push_back(MO);
       Found = true;
     }
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 102249c7816..1bfa23b4b61 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -450,7 +450,7 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
     case 'I':
       // Write 'i' if an integer constant, otherwise nothing.  Used to print
       // addi vs add, etc.
-      if (MI->getOperand(OpNo).isImm())
+      if (MI->getOperand(OpNo).isImmediate())
         O << "i";
       return false;
     }
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index 4286f01b30d..5220c642cb0 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -129,7 +129,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
       unsigned MBBStartOffset = 0;
       for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
            I != E; ++I) {
-        if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
+        if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) {
           MBBStartOffset += getNumBytesForInstruction(I);
           continue;
         }
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 11b5b635db4..e4508e43eb2 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -68,13 +68,13 @@ bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
     for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
       if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
         MachineOperand &MO = MI->getOperand(i);
-        if (MO.isReg()) {
+        if (MO.isRegister()) {
           MO.setReg(Pred[j].getReg());
           MadeChange = true;
-        } else if (MO.isImm()) {
+        } else if (MO.isImmediate()) {
           MO.setImm(Pred[j].getImmedValue());
           MadeChange = true;
-        } else if (MO.isMBB()) {
+        } else if (MO.isMachineBasicBlock()) {
           MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
           MadeChange = true;
         }
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index 3d54d69ebb5..e53edff65d8 100644
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -547,7 +547,7 @@ bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
     case 'h': // Print QImode high register
     case 'w': // Print HImode register
     case 'k': // Print SImode register
-      if (MI->getOperand(OpNo).isReg())
+      if (MI->getOperand(OpNo).isRegister())
         return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
       printOperand(MI, OpNo);
       return false;
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 615c05533f3..ac6d6145e51 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -220,7 +220,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
     SmallVector<unsigned, 8> DeadRegs;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       const MachineOperand &MO = MI->getOperand(i);
-      if (MO.isReg() && MO.isDead())
+      if (MO.isRegister() && MO.isDead())
         DeadRegs.push_back(MO.getReg());
     }
 
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 774531e7a7b..557f07e8b40 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -291,9 +291,9 @@ void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
 
 static const MachineInstrBuilder &FuseInstrAddOperand(MachineInstrBuilder &MIB,
                                                       MachineOperand &MO) {
-  if (MO.isReg())
+  if (MO.isRegister())
     MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
-  else if (MO.isImm())
+  else if (MO.isImmediate())
     MIB = MIB.addImm(MO.getImm());
   else if (MO.isFrameIndex())
     MIB = MIB.addFrameIndex(MO.getFrameIndex());
@@ -340,7 +340,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (i == OpNo) {
-      assert(MO.isReg() && "Expected to fold into reg operand!");
+      assert(MO.isRegister() && "Expected to fold into reg operand!");
       unsigned NumAddrOps = MOs.size();
       for (unsigned i = 0; i != NumAddrOps; ++i)
         MIB = FuseInstrAddOperand(MIB, MOs[i]);
@@ -440,8 +440,8 @@ X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
   // instruction is different than folding it other places.  It requires
   // replacing the *two* registers with the memory location.
   if (isTwoAddr && NumOps >= 2 && i < 2 &&
-      MI->getOperand(0).isReg() && 
-      MI->getOperand(1).isReg() &&
+      MI->getOperand(0).isRegister() && 
+      MI->getOperand(1).isRegister() &&
       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 
     static const TableEntry OpcodeTable[] = {
       { X86::ADC32ri,     X86::ADC32mi },
@@ -1528,7 +1528,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
   if (RetOpcode == X86::EH_RETURN) {
     MBBI = prior(MBB.end());
     MachineOperand &DestAddr  = MBBI->getOperand(0);
-    assert(DestAddr.isReg() && "Offset should be in register!");
+    assert(DestAddr.isRegister() && "Offset should be in register!");
     BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
       addReg(DestAddr.getReg());
   }