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Hooks for predication support.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-16 02:01:49 +00:00
parent 4e654852f1
commit 9307292ae2
4 changed files with 39 additions and 0 deletions
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22
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -423,6 +423,28 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
return false;
}
bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_PREDICATED)
return true;
unsigned Opc = MI->getOpcode();
return Opc == ARM::B || Opc == ARM::tB;
}
void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const {
unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) {
MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
MI->addImmOperand(Cond[0].getImmedValue());
return;
}
MachineOperand *PMO = MI->findFirstPredOperand();
PMO->setImm(Cond[0].getImmedValue());
}
/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,

5
lib/Target/ARM/ARMInstrInfo.h
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@ -102,6 +102,11 @@ public:
const std::vector<MachineOperand> &Cond) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
// Predication support.
virtual bool isPredicatable(MachineInstr *MI) const;
virtual void PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const;
};
// Utility routines

11
lib/Target/ARM/ARMTargetMachine.cpp
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@ -17,6 +17,7 @@
#include "ARM.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Target/TargetOptions.h"
@ -24,6 +25,8 @@ using namespace llvm;
static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
cl::desc("Disable load store optimization pass"));
static cl::opt<bool> EnableIfConversion("enable-arm-if-conversion", cl::Hidden,
cl::desc("Enable if-conversion pass"));
namespace {
// Register the target.
@ -85,6 +88,14 @@ bool ARMTargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) {
return false;
}
bool ARMTargetMachine::addPostRegAlloc(FunctionPassManager &PM, bool Fast) {
if (Fast || !EnableIfConversion || Subtarget.isThumb())
return false;
PM.add(createIfConverterPass());
return true;
}
bool ARMTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
if (!Fast && !DisableLdStOpti && !Subtarget.isThumb())

1
lib/Target/ARM/ARMTargetMachine.h
View File

@ -53,6 +53,7 @@ public:
// Pass Pipeline Configuration
virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast);
virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);