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Stylistic modifications. No functionality changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nicolas Geoffray 2008-03-10 17:46:45 +00:00
parent 45bcbf491c
commit 9348c69dcf
1 changed files with 39 additions and 44 deletions
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83
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -386,30 +386,27 @@ static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
// backend currently only uses CR1EQ as an individual bit, this should // backend currently only uses CR1EQ as an individual bit, this should
// not cause any bug. If we need other uses of CR bits, the following // not cause any bug. If we need other uses of CR bits, the following
// code may be invalid. // code may be invalid.
unsigned Reg = 0;
if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN) if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
return StoreRegToStackSlot(TII, PPC::CR0, isKill, FrameIdx, Reg = PPC::CR0;
PPC::CRRCRegisterClass, NewMIs);
else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN) else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
return StoreRegToStackSlot(TII, PPC::CR1, isKill, FrameIdx, Reg = PPC::CR1;
PPC::CRRCRegisterClass, NewMIs); else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN) Reg = PPC::CR2;
return StoreRegToStackSlot(TII, PPC::CR2, isKill, FrameIdx, else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
PPC::CRRCRegisterClass, NewMIs); Reg = PPC::CR3;
if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN) else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
return StoreRegToStackSlot(TII, PPC::CR3, isKill, FrameIdx, Reg = PPC::CR4;
PPC::CRRCRegisterClass, NewMIs); else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN) Reg = PPC::CR5;
return StoreRegToStackSlot(TII, PPC::CR4, isKill, FrameIdx, else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
PPC::CRRCRegisterClass, NewMIs); Reg = PPC::CR6;
if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN) else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
return StoreRegToStackSlot(TII, PPC::CR5, isKill, FrameIdx, Reg = PPC::CR7;
PPC::CRRCRegisterClass, NewMIs);
if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN) return StoreRegToStackSlot(TII, Reg, isKill, FrameIdx,
return StoreRegToStackSlot(TII, PPC::CR6, isKill, FrameIdx, PPC::CRRCRegisterClass, NewMIs);
PPC::CRRCRegisterClass, NewMIs);
if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
return StoreRegToStackSlot(TII, PPC::CR7, isKill, FrameIdx,
PPC::CRRCRegisterClass, NewMIs);
} else if (RC == PPC::VRRCRegisterClass) { } else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit: // We don't have indexed addressing for vector loads. Emit:
// R0 = ADDI FI# // R0 = ADDI FI#
@ -533,30 +530,28 @@ static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0)); NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
} else if (RC == PPC::CRBITRCRegisterClass) { } else if (RC == PPC::CRBITRCRegisterClass) {
unsigned Reg = 0;
if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN) if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
return LoadRegFromStackSlot(TII, PPC::CR0, FrameIdx, Reg = PPC::CR0;
PPC::CRRCRegisterClass, NewMIs);
else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN) else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
return LoadRegFromStackSlot(TII, PPC::CR1, FrameIdx, Reg = PPC::CR1;
PPC::CRRCRegisterClass, NewMIs); else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN) Reg = PPC::CR2;
return LoadRegFromStackSlot(TII, PPC::CR2, FrameIdx, else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
PPC::CRRCRegisterClass, NewMIs); Reg = PPC::CR3;
if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN) else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
return LoadRegFromStackSlot(TII, PPC::CR3, FrameIdx, Reg = PPC::CR4;
PPC::CRRCRegisterClass, NewMIs); else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN) Reg = PPC::CR5;
return LoadRegFromStackSlot(TII, PPC::CR4, FrameIdx, else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
PPC::CRRCRegisterClass, NewMIs); Reg = PPC::CR6;
if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN) else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
return LoadRegFromStackSlot(TII, PPC::CR5, FrameIdx, Reg = PPC::CR7;
PPC::CRRCRegisterClass, NewMIs);
if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN) return LoadRegFromStackSlot(TII, Reg, FrameIdx,
return LoadRegFromStackSlot(TII, PPC::CR6, FrameIdx, PPC::CRRCRegisterClass, NewMIs);
PPC::CRRCRegisterClass, NewMIs);
if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
return LoadRegFromStackSlot(TII, PPC::CR7, FrameIdx,
PPC::CRRCRegisterClass, NewMIs);
} else if (RC == PPC::VRRCRegisterClass) { } else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit: // We don't have indexed addressing for vector loads. Emit:
// R0 = ADDI FI# // R0 = ADDI FI#