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Now that the ISel is available, it's possible to create a default instruction

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scheduler creator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29452 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2006-08-01 19:14:14 +00:00
parent 1ed3af11b5
commit 9373beba60
4 changed files with 30 additions and 17 deletions
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1
include/llvm/CodeGen/LinkAllCodegenComponents.h
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@ -38,6 +38,7 @@ namespace {
(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
(void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
(void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
(void) llvm::createDefaultScheduler(NULL, NULL, NULL);
}
} ForceCodegenLinking; // Force link by creating a global definition.

5
include/llvm/CodeGen/ScheduleDAG.h
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@ -258,6 +258,11 @@ namespace llvm {
SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
MachineBasicBlock *BB);
}
#endif

2
include/llvm/CodeGen/SelectionDAGISel.h
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@ -41,6 +41,8 @@ public:
MachineBasicBlock *BB;
SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
TargetLowering &getTargetLowering() { return TLI; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const;

39
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -68,7 +68,8 @@ namespace {
cl::desc("Instruction schedulers available:"));
static RegisterScheduler
defaultListDAGScheduler("default", " Best scheduler for the target", NULL);
defaultListDAGScheduler("default", " Best scheduler for the target",
createDefaultScheduler);
} // namespace
namespace {
@ -123,6 +124,24 @@ namespace {
}
namespace llvm {
//===--------------------------------------------------------------------===//
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
MachineBasicBlock *BB) {
TargetLowering &TLI = IS->getTargetLowering();
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
return createTDListDAGScheduler(IS, DAG, BB);
} else {
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
return createBURRListDAGScheduler(IS, DAG, BB);
}
}
//===--------------------------------------------------------------------===//
/// FunctionLoweringInfo - This contains information that is global to a
/// function that is used when lowering a region of the function.
@ -3614,22 +3633,8 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
RegisterScheduler::getDefault();
if (!Ctor) {
if (std::string("default") == std::string(ISHeuristic)) {
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
Ctor = RegisterScheduler::FindCtor("list-td");
else {
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
Ctor = RegisterScheduler::FindCtor("list-burr");
}
assert(Ctor && "Default instruction scheduler not present");
if (!Ctor) Ctor = RegisterScheduler::FindCtor("none");
} else {
Ctor = RegisterScheduler::FindCtor(ISHeuristic);
}
RegisterScheduler::setDefault(Ctor);
Ctor = RegisterScheduler::FindCtor(ISHeuristic);
RegisterScheduler::setDefault(Ctor);
}
assert(Ctor && "No instruction scheduler found");