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ARM64: add extra patterns for scalar shifts

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205209 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-03-31 15:46:46 +00:00
parent 812a174ba4
commit 93b3fcae28
3 changed files with 34 additions and 6 deletions
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18
lib/Target/ARM64/ARM64InstrFormats.td
View File

@ -6651,22 +6651,28 @@ multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode> {
def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
FPR64, FPR64, vecshiftR64, asm,
[(set (v1i64 FPR64:$Rd),
(OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
[(set (i64 FPR64:$Rd),
(OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
let Inst{21-16} = imm{5-0};
}
def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
(!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
}
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode = null_frag> {
def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
FPR64, FPR64, vecshiftR64, asm,
[(set (v1i64 FPR64:$dst),
(OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
(i32 vecshiftR64:$imm)))]> {
[(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
(i32 vecshiftR64:$imm)))]> {
let Inst{21-16} = imm{5-0};
}
def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
(i32 vecshiftR64:$imm))),
(!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
vecshiftR64:$imm)>;
}
multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,

14
test/CodeGen/ARM64/vshr.ll
View File

@ -46,4 +46,18 @@ entry:
ret <8 x i16> %shr
}
define <1 x i64> @sshr_v1i64(<1 x i64> %A) nounwind {
; CHECK-LABEL: sshr_v1i64:
; CHECK: sshr d0, d0, #63
%tmp3 = ashr <1 x i64> %A, < i64 63 >
ret <1 x i64> %tmp3
}
define <1 x i64> @ushr_v1i64(<1 x i64> %A) nounwind {
; CHECK-LABEL: ushr_v1i64:
; CHECK: ushr d0, d0, #63
%tmp3 = lshr <1 x i64> %A, < i64 63 >
ret <1 x i64> %tmp3
}
attributes #0 = { nounwind }

8
test/CodeGen/ARM64/vsra.ll
View File

@ -140,3 +140,11 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
%tmp4 = add <2 x i64> %tmp1, %tmp3
ret <2 x i64> %tmp4
}
define <1 x i64> @vsra_v1i64(<1 x i64> %A, <1 x i64> %B) nounwind {
; CHECK-LABEL: vsra_v1i64:
; CHECK: ssra d0, d1, #63
%tmp3 = ashr <1 x i64> %B, < i64 63 >
%tmp4 = add <1 x i64> %A, %tmp3
ret <1 x i64> %tmp4
}