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[PowerPC] Mark P9 scheduling model complete
This patch just adds the missing information to the P9 scheduling model to allow the model to be marked as complete. The model has been verified against P9 documentation. The model was verified with utils/schedcover.py. Differential Revision: https://reviews.llvm.org/D35695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stefan Pintilie
parent
0b345b230b
commit
93f389e6f1
@ -12,11 +12,29 @@
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// is listed here. Instructions in this file belong to itinerary classes that
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// have instructions with different resource requirements.
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//
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// The makeup of the P9 CPU is modeled as follows:
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// - Each CPU is made up of two superslices.
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// - Each superslice is made up of two slices. Therefore, there are 4 slices
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// for each CPU.
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// - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
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// - Each CPU has:
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// - One CY (Crypto) unit P9_CY_*
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// - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
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// - Two PM (Permute) units. One on each superslice. P9_PM_*
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// - Two DIV (Fixed Point Divide) units. One on each superslize. P9_DIV_*
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// - Four ALU (Fixed Point Arithmetic) units. One on each slice. P9_ALU_*
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// - Four DP (Floating Point) units. One on each slice. P9_DP_*
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// This also includes fixed point multiply add.
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// - Four AGEN (Address Generation) units. One for each slice. P9_AGEN_*
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// - Four Load/Store Queues. P9_LS_*
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// - Each set of instructions will require a number of these resources.
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//===----------------------------------------------------------------------===//
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// Two cycle ALU vector operation that uses an entire superslice.
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// Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
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// (EXECE, EXECO) and all three dispatches (DISP) to the given superslice.
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def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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DISP_1C, DISP_1C],
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DISP_1C, DISP_1C, DISP_1C],
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(instrs
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VADDCUW,
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VADDUBM,
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@ -26,47 +44,41 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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VAND,
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VANDC,
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VCMPEQUB,
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VCMPEQUBo,
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VCMPEQUD,
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VCMPEQUDo,
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VCMPEQUH,
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VCMPEQUHo,
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VCMPEQUW,
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VCMPEQUWo,
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VCMPGTSB,
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VCMPGTSBo,
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VCMPGTSD,
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VCMPGTSDo,
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VCMPGTSH,
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VCMPGTSHo,
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VCMPGTSW,
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VCMPGTSWo,
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VCMPGTUB,
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VCMPGTUBo,
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VCMPGTUD,
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VCMPGTUDo,
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VCMPGTUH,
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VCMPGTUHo,
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VCMPGTUW,
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VCMPGTUWo,
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VCMPNEB,
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VCMPNEBo,
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VCMPNEH,
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VCMPNEHo,
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VCMPNEW,
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VCMPNEWo,
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VCMPNEZB,
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VCMPNEZBo,
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VCMPNEZH,
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VCMPNEZHo,
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VCMPNEZW,
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VCMPNEZWo,
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VEQV,
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VEXTSB2D,
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VEXTSB2W,
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VEXTSH2D,
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VEXTSH2W,
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VEXTSW2D,
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VRLB,
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VRLD,
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VRLDMI,
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VRLDNM,
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VRLH,
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VRLW,
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VRLWMI,
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VRLWNM,
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VSRAB,
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VSRAD,
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VSRAH,
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VSRAW,
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VSRB,
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VSRD,
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VSRH,
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VSRW,
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VSLB,
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VSLD,
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VSLH,
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VSLW,
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VMRGEW,
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VMRGOW,
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VNAND,
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@ -77,9 +89,7 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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VORC,
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VPOPCNTB,
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VPOPCNTH,
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VPOPCNTW,
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VSEL,
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VSUBCUW,
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VSUBUBM,
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VSUBUDM,
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VSUBUHM,
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@ -98,6 +108,8 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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XVNEGDP,
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XVNEGSP,
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XVXEXPDP,
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XVIEXPSP,
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XVXEXPSP,
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XXLAND,
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XXLANDC,
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XXLEQV,
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@ -107,74 +119,29 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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XXLORf,
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XXLORC,
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XXLXOR,
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XXSEL
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)>;
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def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instrs
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XXSEL,
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XSABSQP,
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XSCPSGNQP,
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XSIEXPQP,
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XSNABSQP,
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XSNEGQP,
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XSXEXPQP,
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XSABSDP,
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XSCPSGNDP,
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XSIEXPDP,
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XSNABSDP,
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XSNEGDP,
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XSXEXPDP
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XSXEXPQP
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)>;
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def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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// Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
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// slingle slice. However, since it is Restricted it requires all 3 dispatches
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// (DISP) for that superslice.
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def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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FCMPUS,
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FCMPUD,
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XSTSTDCDP,
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XSTSTDCSP
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)>;
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VMINSB,
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VMINSD,
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VMINSH,
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VMINSW,
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VMINUB,
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VMINUD,
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VMINUH,
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VMINUW,
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VPOPCNTD,
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VPRTYBD,
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VPRTYBW,
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VRLB,
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VRLD,
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VRLDMI,
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VRLDNM,
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VRLH,
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VRLW,
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VRLWMI,
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VRLWNM,
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VSHASIGMAD,
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VSHASIGMAW,
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VSLB,
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VSLD,
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VSLH,
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VSLW,
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VSRAB,
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VSRAD,
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VSRAH,
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VSRAW,
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VSRB,
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VSRD,
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VSRH,
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VSRW,
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VSUBSBS,
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VSUBSHS,
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VSUBSWS,
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VSUBUBS,
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VSUBUHS,
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VSUBUWS,
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XSCMPEQDP,
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XSCMPEXPDP,
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XSCMPGEDP,
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XSCMPGTDP,
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XSCMPODP,
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XSCMPUDP,
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XSCVSPDPN,
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// Standard Dispatch ALU operation for 3 cycles. Only one slice used.
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def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instrs
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XSMAXCDP,
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XSMAXDP,
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XSMAXJDP,
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@ -183,9 +150,153 @@ def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C
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XSMINJDP,
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XSTDIVDP,
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XSTSQRTDP,
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XSTSTDCDP,
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XSTSTDCSP,
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XSCMPEQDP,
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XSCMPEXPDP,
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XSCMPGEDP,
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XSCMPGTDP,
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XSCMPODP,
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XSCMPUDP,
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XSXSIGDP,
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XSCVSPDPN
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)>;
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// Standard Dispatch ALU operation for 2 cycles. Only one slice used.
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def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instrs
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ADDIStocHA,
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ADDItocL,
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MCRF,
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MCRXRX,
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SLD,
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SRD,
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SRAD,
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SRADI,
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RLDIC,
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XSNABSDP,
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XSXEXPDP,
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XSABSDP,
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XSNEGDP,
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XSCPSGNDP
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)>;
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// Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
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// slingle slice. However, since it is Restricted it requires all 3 dispatches
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// (DISP) for that superslice.
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def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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RLDCL,
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RLDCR,
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RLDIMI,
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RLDICL,
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RLDICR,
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RLDICL_32_64,
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XSIEXPDP,
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FMR,
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FABSD,
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FABSS,
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FNABSD,
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FNABSS,
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FNEGD,
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FNEGS,
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FCPSGND,
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FCPSGNS
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)>;
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// Three cycle ALU vector operation that uses an entire superslice.
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// Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
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// (EXECE, EXECO) and all three dispatches (DISP) to the given superslice.
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def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C,
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DISP_1C, DISP_1C, DISP_1C],
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(instrs
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VBPERMD,
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VABSDUB,
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VABSDUH,
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VABSDUW,
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VADDUBS,
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VADDUHS,
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VADDUWS,
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VAVGSB,
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VAVGSH,
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VAVGSW,
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VAVGUB,
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VAVGUH,
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VAVGUW,
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VCMPEQFP,
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VCMPEQFPo,
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VCMPGEFP,
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VCMPGEFPo,
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VCMPBFP,
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VCMPBFPo,
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VCMPGTFP,
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VCMPGTFPo,
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VCLZB,
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VCLZD,
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VCLZH,
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VCLZW,
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VCTZB,
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VCTZD,
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VCTZH,
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VCTZW,
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VADDSBS,
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VADDSHS,
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VADDSWS,
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VMINFP,
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VMINSB,
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VMINSD,
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VMINSH,
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VMINSW,
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VMINUB,
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VMINUD,
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VMINUH,
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VMINUW,
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VMAXFP,
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VMAXSB,
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VMAXSD,
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VMAXSH,
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VMAXSW,
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VMAXUB,
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VMAXUD,
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VMAXUH,
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VMAXUW,
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VPOPCNTW,
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VPOPCNTD,
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VPRTYBD,
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VPRTYBW,
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VSHASIGMAD,
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VSHASIGMAW,
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VSUBSBS,
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VSUBSHS,
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VSUBSWS,
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VSUBUBS,
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VSUBUHS,
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VSUBUWS,
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VSUBCUW,
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VCMPGTSB,
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VCMPGTSBo,
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VCMPGTSD,
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VCMPGTSDo,
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VCMPGTSH,
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VCMPGTSHo,
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VCMPGTSW,
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VCMPGTSWo,
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VCMPGTUB,
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VCMPGTUBo,
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VCMPGTUD,
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VCMPGTUDo,
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VCMPGTUH,
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VCMPGTUHo,
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VCMPGTUW,
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VCMPGTUWo,
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VCMPNEBo,
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VCMPNEHo,
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VCMPNEWo,
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VCMPNEZBo,
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VCMPNEZHo,
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VCMPNEZWo,
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VCMPEQUBo,
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VCMPEQUDo,
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VCMPEQUHo,
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VCMPEQUWo,
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XVCMPEQDP,
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XVCMPEQDPo,
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XVCMPEQSP,
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@ -198,7 +309,6 @@ def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C
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XVCMPGTDPo,
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XVCMPGTSP,
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XVCMPGTSPo,
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XVIEXPSP,
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XVMAXDP,
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XVMAXSP,
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XVMINDP,
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@ -209,58 +319,15 @@ def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C
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XVTSQRTSP,
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XVTSTDCDP,
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XVTSTDCSP,
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XVXEXPSP,
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XVXSIGDP,
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XVXSIGSP
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)>;
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def : InstRW<[P9_ALUE_4C, P9_ALUO_4C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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(instrs
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VABSDUB,
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VABSDUH,
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VABSDUW,
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VADDSBS,
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VADDSHS,
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VADDSWS,
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VADDUBS,
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VADDUHS,
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VADDUWS,
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VAVGSB,
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VAVGSH,
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VAVGSW,
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VAVGUB,
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VAVGUH,
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VAVGUW,
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VBPERMD,
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VCLZB,
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VCLZD,
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VCLZH,
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VCLZW,
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VCMPBFP,
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VCMPBFPo,
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VCMPGTFP,
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VCMPGTFPo,
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VCTZB,
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VCTZD,
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VCTZH,
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VCTZW,
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VMAXFP,
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VMAXSB,
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VMAXSD,
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VMAXSH,
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VMAXSW,
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VMAXUB,
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VMAXUD,
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VMAXUH,
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VMAXUW,
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VMINFP,
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VCMPEQFP,
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VCMPEQFPo,
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VCMPGEFP,
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VCMPGEFPo
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)>;
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def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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// 7 cycle DP vector operation that uses an entire superslice.
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// Uses both DP units (the even DPE and odd DPO units), two pipelines
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// (EXECE, EXECO) and all three dispatches (DISP) to the given superslice.
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def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C,
|
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DISP_1C, DISP_1C, DISP_1C],
|
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(instrs
|
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VADDFP,
|
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VCTSXS,
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@ -367,8 +434,47 @@ def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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VSUMSWS
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)>;
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// 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
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// dispatch units for the superslice.
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def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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FRSP,
|
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FRIND,
|
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FRINS,
|
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FRIPD,
|
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FRIPS,
|
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FRIZD,
|
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FRIZS,
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FRIMD,
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FRIMS,
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FRE,
|
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FRES,
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FRSQRTE,
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FRSQRTES,
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FMADDS,
|
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FMADD,
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FMSUBS,
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FMSUB,
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FNMADDS,
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FNMADD,
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FNMSUBS,
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FNMSUB,
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FSELD,
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FSELS,
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FADDS,
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FMULS,
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FMUL,
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FSUBS,
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FCFID,
|
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FCTID,
|
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FCTIDZ,
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FCFIDU,
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FCFIDS,
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FCFIDUS,
|
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FCTIDUZ,
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FCTIWUZ,
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FCTIW,
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FCTIWZ,
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XSMADDADP,
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XSMADDASP,
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XSMADDMDP,
|
||||
@ -389,7 +495,7 @@ def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
XSNMSUBMSP
|
||||
)>;
|
||||
|
||||
|
||||
// 7 cycle DP operation. One DP unit, one EXEC pipeline and two dispatch units.
|
||||
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSADDDP,
|
||||
@ -397,8 +503,10 @@ def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
XSCVDPHP,
|
||||
XSCVDPSP,
|
||||
XSCVDPSXDS,
|
||||
XSCVDPSXDSs,
|
||||
XSCVDPSXWS,
|
||||
XSCVDPUXDS,
|
||||
XSCVDPUXDSs,
|
||||
XSCVDPUXWS,
|
||||
XSCVHPDP,
|
||||
XSCVSPDP,
|
||||
@ -421,7 +529,10 @@ def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
XSCVDPSPN
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
// Three Cycle PM operation. Only one PM unit per superslice so we use the whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
VBPERMQ,
|
||||
VCLZLSBB,
|
||||
@ -469,7 +580,9 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
VSLO,
|
||||
VSLV,
|
||||
VSPLTB,
|
||||
VSPLTBs,
|
||||
VSPLTH,
|
||||
VSPLTHs,
|
||||
VSPLTISB,
|
||||
VSPLTISH,
|
||||
VSPLTISW,
|
||||
@ -498,6 +611,9 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
XXSLDWI,
|
||||
XXSPLTIB,
|
||||
XXSPLTW,
|
||||
XXSPLTWs,
|
||||
XXPERMDI,
|
||||
XXPERMDIs,
|
||||
VADDCUQ,
|
||||
VADDECUQ,
|
||||
VADDEUQM,
|
||||
@ -517,7 +633,10 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
XSXSIGQP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
// 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSADDQP,
|
||||
XSADDQPO,
|
||||
@ -536,7 +655,10 @@ def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
XSSUBQPO
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
// 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSMADDQP,
|
||||
XSMADDQPO,
|
||||
@ -550,45 +672,56 @@ def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
XSNMSUBQPO
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
// 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSDIVQP,
|
||||
XSDIVQPO
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DFU_76C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
// 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DFU_76C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSSQRTQP,
|
||||
XSSQRTQPO
|
||||
)>;
|
||||
|
||||
// Load Operation in IIC_LdStLFD
|
||||
|
||||
// 5 Cycle load uses a single slice.
|
||||
def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXSDX,
|
||||
LXVD2X,
|
||||
LXSIWZX,
|
||||
LXV,
|
||||
LXSD
|
||||
LXVX,
|
||||
LXSD,
|
||||
DFLOADf64
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
// 4 Cycle load uses a single slice.
|
||||
def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
COPY
|
||||
)>;
|
||||
|
||||
// 4 Cycle Restricted load uses a single slice but the dispatch for the whole
|
||||
// superslice.
|
||||
def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFIWZX,
|
||||
LFDX,
|
||||
LFD
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXSSPX,
|
||||
LXSIWAX,
|
||||
LXSSP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
// Cracked Restricted Load instruction.
|
||||
// Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
|
||||
// operations cannot be done at the same time and so their latencies are added.
|
||||
// Full 6 dispatches are required as this is both cracked and restricted.
|
||||
def : InstRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFIWAX,
|
||||
@ -596,14 +729,35 @@ def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
LFS
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
// Cracked Load instruction.
|
||||
// Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
|
||||
// operations cannot be done at the same time and so their latencies are added.
|
||||
// Full 4 dispatches are required as this is a cracked instruction.
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXSSPX,
|
||||
LXSIWAX,
|
||||
LXSSP,
|
||||
DFLOADf32
|
||||
)>;
|
||||
|
||||
// Cracked Load that requires the PM resource.
|
||||
// Since the Load and the PM cannot be done at the same time the latencies are
|
||||
// added. Requires 8 cycles.
|
||||
// Since the PM requires the full superslice we need both EXECE, EXECO pipelines
|
||||
// as well as 3 dispatches for the PM. The Load requires the remaining 2
|
||||
// dispatches.
|
||||
def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXVDSX,
|
||||
LXVWSX,
|
||||
LXVW4X
|
||||
)>;
|
||||
|
||||
// Store Operations in IIC_LdStSTFD.
|
||||
|
||||
// Single slice Restricted store operation. The restricted operation requires
|
||||
// all three dispatches for the superslice.
|
||||
def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
STFS,
|
||||
@ -613,74 +767,83 @@ def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
STFDX,
|
||||
STXSDX,
|
||||
STXSSPX,
|
||||
STXSIWX
|
||||
STXSIWX,
|
||||
DFSTOREf32,
|
||||
DFSTOREf64
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C],
|
||||
// Store operation that requires the whole superslice.
|
||||
def : InstRW<[P9_LS_1C, IP_EXECE_1C, IP_EXECO_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
STXVD2X,
|
||||
STXVW4X
|
||||
)>;
|
||||
|
||||
|
||||
// Divide Operations in IIC_IntDivW, IIC_IntDivD.
|
||||
|
||||
def : InstRW<[P9_DIV_16C_8, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
// 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVW,
|
||||
DIVWU
|
||||
DIVWU,
|
||||
MODSW
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DIV_24C_8, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
// 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVWE,
|
||||
DIVD,
|
||||
DIVWEU,
|
||||
DIVDU
|
||||
DIVDU,
|
||||
MODSD,
|
||||
MODUD,
|
||||
MODUW
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DIV_40C_8, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
// 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_DIV_40C_8, IP_EXECO_1C, IP_EXECE_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVDE,
|
||||
DIVDEU
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
|
||||
// and one full superslice for the DIV operation since there is only one DIV
|
||||
// per superslice. Latency of DIV plus ALU is 26.
|
||||
def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVWEo,
|
||||
DIVWEUo
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
// Cracked DIV and ALU operation. Requires one full slice for the ALU operation
|
||||
// and one full superslice for the DIV operation since there is only one DIV
|
||||
// per superslice. Latency of DIV plus ALU is 42.
|
||||
def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVDEo,
|
||||
DIVDEUo
|
||||
)>;
|
||||
|
||||
// Rotate Operations in IIC_IntRotateD, IIC_IntRotateDI
|
||||
def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
SLD,
|
||||
SRD,
|
||||
SRAD,
|
||||
SRADI,
|
||||
RLDIC
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
RLDCL,
|
||||
RLDCR,
|
||||
RLDIMI,
|
||||
RLDICL,
|
||||
RLDICR,
|
||||
RLDICL_32_64
|
||||
)>;
|
||||
|
||||
// CR access instructions in _BrMCR, IIC_BrMCRX.
|
||||
|
||||
// Cracked, restricted, ALU operations.
|
||||
// Here the two ALU ops can actually be done in parallel and therefore the
|
||||
// latencies are not added together. Otherwise this is like having two
|
||||
// instructions running together on two pipelines and 6 dispatches.
|
||||
// ALU ops are 2 cycles each.
|
||||
def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
@ -690,13 +853,12 @@ def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
MTCRF8
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_5C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
MCRF,
|
||||
MCRXRX
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_5C, P9_ALU_5C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
// Cracked, restricted, ALU operations.
|
||||
// Here the two ALU ops can actually be done in parallel and therefore the
|
||||
// latencies are not added together. Otherwise this is like having two
|
||||
// instructions running together on two pipelines and 6 dispatches.
|
||||
// ALU ops are 3 cycles each.
|
||||
def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
MCRFS
|
||||
@ -704,93 +866,57 @@ def : InstRW<[P9_ALU_5C, P9_ALU_5C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
|
||||
// FP Div instructions in IIC_FPDivD and IIC_FPDivS.
|
||||
|
||||
// 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
|
||||
def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FDIV,
|
||||
FDIV
|
||||
)>;
|
||||
|
||||
// 33 Cycle DP Instruction. Takes one slice and 2 dispatches.
|
||||
def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSDIVDP
|
||||
)>;
|
||||
|
||||
// 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
|
||||
def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FDIVS,
|
||||
FDIVS
|
||||
)>;
|
||||
|
||||
// 22 Cycle DP Instruction. Takes one slice and 2 dispatches.
|
||||
def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSDIVSP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_24C_8, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
// 24 Cycle DP Vector Instruction. Takes one full superslice.
|
||||
// Includes both EXECE, EXECO pipelines and all 3 dispatches for the given
|
||||
// superslice.
|
||||
def : InstRW<[P9_DPE_24C_8, P9_DPO_24C_8, IP_EXECE_1C, IP_EXECO_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XVDIVSP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_33C_8, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
// 33 Cycle DP Vector Instruction. Takes one full superslice.
|
||||
// Includes both EXECE, EXECO pipelines and all 3 dispatches for the given
|
||||
// superslice.
|
||||
def : InstRW<[P9_DPE_33C_8, P9_DPO_33C_8, IP_EXECE_1C, IP_EXECO_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XVDIVDP
|
||||
)>;
|
||||
|
||||
// FP Instructions in IIC_FPGeneral, IIC_FPFused
|
||||
|
||||
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FRSP,
|
||||
FRIND,
|
||||
FRINS,
|
||||
FRIPD,
|
||||
FRIPS,
|
||||
FRIZD,
|
||||
FRIZS,
|
||||
FRIMD,
|
||||
FRIMS,
|
||||
FRE,
|
||||
FRES,
|
||||
FRSQRTE,
|
||||
FRSQRTES,
|
||||
FMADDS,
|
||||
FMADD,
|
||||
FMSUBS,
|
||||
FMSUB,
|
||||
FNMADDS,
|
||||
FNMADD,
|
||||
FNMSUBS,
|
||||
FNMSUB,
|
||||
FSELD,
|
||||
FSELS,
|
||||
FADDS,
|
||||
FMULS,
|
||||
FMUL,
|
||||
FSUBS,
|
||||
FCFID,
|
||||
FCTID,
|
||||
FCTIDZ,
|
||||
FCFIDU,
|
||||
FCFIDS,
|
||||
FCFIDUS,
|
||||
FCTIDUZ,
|
||||
FCTIWUZ,
|
||||
FCTIW,
|
||||
FCTIWZ
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FMR,
|
||||
FABSD,
|
||||
FABSS,
|
||||
FNABSD,
|
||||
FNABSS,
|
||||
FNEGD,
|
||||
FNEGS,
|
||||
FCPSGND,
|
||||
FCPSGNS
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FCMPUS,
|
||||
FCMPUD
|
||||
)>;
|
||||
|
||||
// Load instructions in IIC_LdStLFDU and IIC_LdStLFDUX.
|
||||
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, P9_ALU_2C,
|
||||
// Instruction cracked into three pieces. One Load and two ALU operations.
|
||||
// The Load and one of the ALU ops cannot be run at the same time and so the
|
||||
// latencies are added together for 6 cycles. The remainaing ALU is 2 cycles.
|
||||
// Both the load and the ALU that depends on it are restricted and so they take
|
||||
// a total of 6 dispatches. The final 2 dispatches come from the second ALU op.
|
||||
// The two EXEC pipelines are for the 2 ALUs while the AGEN is for the load.
|
||||
def : InstRW<[P9_LoadAndALUOp_6C, P9_ALU_2C,
|
||||
IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
@ -799,10 +925,32 @@ def : InstRW<[P9_LoadAndALUOp_7C, P9_ALU_2C,
|
||||
LFSUX
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LS_5C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
// Cracked instruction made up of a Load and an ALU. The ALU does not depend on
|
||||
// the load and so it can be run at the same time as the load. The load is also
|
||||
// restricted. 3 dispatches are from the restricted load while the other two
|
||||
// are from the ALU. The AGEN pipeline is from the load and the EXEC pipeline
|
||||
// is required for the ALU.
|
||||
def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFDU,
|
||||
LFDUX
|
||||
)>;
|
||||
|
||||
// Crypto Instructions
|
||||
|
||||
// 6 Cycle CY operation. Only one CY unit per CPU so we use a whole
|
||||
// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
|
||||
// dispatches.
|
||||
def : InstRW<[P9_CY_6C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
VPMSUMB,
|
||||
VPMSUMD,
|
||||
VPMSUMH,
|
||||
VPMSUMW,
|
||||
VCIPHER,
|
||||
VCIPHERLAST,
|
||||
VNCIPHER,
|
||||
VNCIPHERLAST,
|
||||
VSBOX
|
||||
)>;
|
||||
|
||||
@ -2101,4 +2101,5 @@ class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
|
||||
let PPC64 = 0;
|
||||
let Pattern = pattern;
|
||||
let Inst{31-0} = 0;
|
||||
let hasNoSchedulingInfo = 1;
|
||||
}
|
||||
|
||||
@ -3951,6 +3951,7 @@ class PPCAsmPseudo<string asm, dag iops>
|
||||
let AsmString = asm;
|
||||
let isAsmParserOnly = 1;
|
||||
let isPseudo = 1;
|
||||
let hasNoSchedulingInfo = 1;
|
||||
}
|
||||
|
||||
def : InstAlias<"sc", (SC 0)>;
|
||||
|
||||
@ -22,7 +22,9 @@ def P9Model : SchedMachineModel {
|
||||
// Try to make sure we have at least 10 dispatch groups in a loop.
|
||||
let LoopMicroOpBufferSize = 60;
|
||||
|
||||
let CompleteModel = 0;
|
||||
let CompleteModel = 1;
|
||||
|
||||
let UnsupportedFeatures = [HasQPX];
|
||||
|
||||
}
|
||||
|
||||
@ -68,6 +70,10 @@ let SchedModel = P9Model in {
|
||||
def LS : ProcResource<4>;
|
||||
def PM : ProcResource<2>;
|
||||
def DFU : ProcResource<1>;
|
||||
def BR : ProcResource<1> {
|
||||
let BufferSize = 16;
|
||||
}
|
||||
def CY : ProcResource<1>;
|
||||
|
||||
def TestGroup : ProcResGroup<[ALU, DP]>;
|
||||
|
||||
@ -145,6 +151,10 @@ let SchedModel = P9Model in {
|
||||
let Latency = 6;
|
||||
}
|
||||
|
||||
def P9_DIV_12C : SchedWriteRes<[DIV]> {
|
||||
let Latency = 12;
|
||||
}
|
||||
|
||||
def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 16;
|
||||
@ -190,6 +200,16 @@ let SchedModel = P9Model in {
|
||||
let Latency = 24;
|
||||
}
|
||||
|
||||
def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 24;
|
||||
}
|
||||
|
||||
def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 24;
|
||||
}
|
||||
|
||||
def P9_DP_26C_5 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [5];
|
||||
let Latency = 22;
|
||||
@ -205,6 +225,16 @@ let SchedModel = P9Model in {
|
||||
let Latency = 33;
|
||||
}
|
||||
|
||||
def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 33;
|
||||
}
|
||||
|
||||
def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 33;
|
||||
}
|
||||
|
||||
def P9_DP_36C_10 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [10];
|
||||
let Latency = 36;
|
||||
@ -248,11 +278,25 @@ let SchedModel = P9Model in {
|
||||
let Latency = 76;
|
||||
let ResourceCycles = [62];
|
||||
}
|
||||
|
||||
def P9_BR_2C : SchedWriteRes<[BR]> {
|
||||
let Latency = 2;
|
||||
}
|
||||
|
||||
def P9_BR_5C : SchedWriteRes<[BR]> {
|
||||
let Latency = 5;
|
||||
}
|
||||
|
||||
def P9_CY_6C : SchedWriteRes<[CY]> {
|
||||
let Latency = 6;
|
||||
}
|
||||
|
||||
// ***************** WriteSeq Definitions *****************
|
||||
|
||||
def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
|
||||
def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
|
||||
def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
|
||||
def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
|
||||
def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
|
||||
def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
|
||||
def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
|
||||
@ -260,19 +304,32 @@ let SchedModel = P9Model in {
|
||||
|
||||
// ***************** Defining Itinerary Class Resources *****************
|
||||
|
||||
// The following itineraries are fully covered by the InstRW definitions in
|
||||
// P9InstrResources.td so aren't listed here.
|
||||
// IIC_FPDivD, IIC_FPDivS, IIC_FPFused, IIC_IntDivD, IIC_LdStLFDU,
|
||||
// IIC_LdStLFDUX
|
||||
|
||||
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_IntSimple, IIC_IntGeneral]>;
|
||||
[IIC_IntSimple, IIC_IntGeneral, IIC_IntRFID,
|
||||
IIC_IntRotateD, IIC_IntRotateDI, IIC_IntTrapD,
|
||||
IIC_SprRFI]>;
|
||||
|
||||
def : ItinRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_IntTrapW]>;
|
||||
|
||||
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_IntISEL, IIC_IntRotate, IIC_IntShift]>;
|
||||
|
||||
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntCompare]>;
|
||||
|
||||
def : ItinRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
|
||||
DISP_1C, DISP_1C], [IIC_VecGeneral, IIC_FPCompare]>;
|
||||
|
||||
def : ItinRW<[P9_DP_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_IntMulHW, IIC_IntMulHWU, IIC_IntMulLI]>;
|
||||
[IIC_IntMulHW, IIC_IntMulHWU, IIC_IntMulLI, IIC_IntMulHD]>;
|
||||
|
||||
def : ItinRW<[P9_LS_5C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLoad, IIC_LdStLD]>;
|
||||
[IIC_LdStLoad, IIC_LdStLD, IIC_LdStLFD]>;
|
||||
|
||||
def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
@ -300,12 +357,18 @@ let SchedModel = P9Model in {
|
||||
def : ItinRW<[P9_LS_4C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLWARX, IIC_LdStLDARX, IIC_LdStLMW]>;
|
||||
|
||||
def : ItinRW<[P9_LS_4C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStCOPY, IIC_SprABORT, IIC_LdStPASTE, IIC_LdStDCBF,
|
||||
IIC_LdStICBI, IIC_LdStSync, IIC_SprISYNC, IIC_SprMSGSYNC,
|
||||
IIC_SprSLBIA, IIC_SprSLBSYNC, IIC_SprTLBSYNC]>;
|
||||
|
||||
def : ItinRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStSTFD, IIC_LdStSTD, IIC_LdStStore]>;
|
||||
|
||||
def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStSTDU, IIC_LdStSTDUX]>;
|
||||
[IIC_LdStSTDU, IIC_LdStSTDUX, IIC_LdStStoreUpd, IIC_SprSLBIEG,
|
||||
IIC_SprTLBIA, IIC_SprTLBIE]>;
|
||||
|
||||
def : ItinRW<[P9_StoreAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
@ -315,20 +378,44 @@ let SchedModel = P9Model in {
|
||||
[IIC_BrCR, IIC_IntMTFSB0]>;
|
||||
|
||||
def : ItinRW<[P9_ALUOpAndALUOp_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C], [IIC_SprMFCR, IIC_SprMFCRF]>;
|
||||
IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_SprMFCR, IIC_SprMFCRF, IIC_BrMCR, IIC_BrMCRX, IIC_IntMFFS]>;
|
||||
|
||||
def : ItinRW<[P9_BR_2C, DISP_1C], [IIC_BrB]>;
|
||||
def : ItinRW<[P9_BR_5C, DISP_1C], [IIC_SprMFSPR]>;
|
||||
|
||||
// This class should be broken down to instruction level, once some missing
|
||||
// info is obtained.
|
||||
def : ItinRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C], [IIC_SprMTSPR]>;
|
||||
|
||||
def : ItinRW<[P9_DP_7C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C], [IIC_FPGeneral, IIC_FPAddSub]>;
|
||||
def : ItinRW<[P9_LoadAndLoadOp_8C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_SprSLBIE, IIC_SprSLBMFEE, IIC_SprSLBMFEV, IIC_SprSLBMTE,
|
||||
IIC_SprTLBIEL]>;
|
||||
|
||||
// IIC_VecFP is added here although many instructions with that itinerary
|
||||
// use very different resources. It would appear that instructions were
|
||||
// given that itinerary rather carelessly over time. Specific instructions
|
||||
// that use different resources are listed in various InstrRW classes.
|
||||
def : ItinRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_FPGeneral, IIC_FPAddSub, IIC_VecFP]>;
|
||||
|
||||
def : ItinRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C,
|
||||
DISP_1C, DISP_1C], [IIC_VecFPCompare]>;
|
||||
|
||||
def : ItinRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
[IIC_VecPerm]>;
|
||||
|
||||
def : ItinRW<[P9_DP_36C_10, IP_EXEC_1C], [IIC_FPSqrtD]>;
|
||||
def : ItinRW<[P9_DP_26C_5, P9_DP_26C_5, IP_EXEC_1C, IP_EXEC_1C], [IIC_FPSqrtS]>;
|
||||
|
||||
def : ItinRW<[P9_DIV_12C, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
[IIC_SprMFMSR, IIC_SprMFPMR, IIC_SprMFSR, IIC_SprMFTB,
|
||||
IIC_SprMTMSR, IIC_SprMTMSRD, IIC_SprMTPMR, IIC_SprMTSR]>;
|
||||
|
||||
def : ItinRW<[], [IIC_SprSTOP]>;
|
||||
|
||||
include "P9InstrResources.td"
|
||||
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user