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XCore target: Fix llvm.eh.return and EH info register handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lytton
parent
eb720cc3a1
commit
9409825b57
@ -25,8 +25,11 @@
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include <algorithm> // std::sort
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using namespace llvm;
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static const unsigned FramePtr = XCore::R10;
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@ -115,21 +118,58 @@ static void IfNeededLDAWSP(MachineBasicBlock &MBB,
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/// Creates an ordered list of registers that are spilled
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/// during the emitPrologue/emitEpilogue.
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/// Registers are ordered according to their frame offset.
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static void GetSpillList(SmallVectorImpl<std::pair<unsigned,int> > &SpillList,
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/// As offsets are negative, the largest offsets will be first.
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static void GetSpillList(SmallVectorImpl<std::pair<int,unsigned> > &SpillList,
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MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
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bool fetchLR, bool fetchFP) {
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int LRSpillOffset = fetchLR? MFI->getObjectOffset(XFI->getLRSpillSlot()) : 0;
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int FPSpillOffset = fetchFP? MFI->getObjectOffset(XFI->getFPSpillSlot()) : 0;
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if (fetchLR && fetchFP && LRSpillOffset > FPSpillOffset) {
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SpillList.push_back(std::pair<unsigned, int>(XCore::LR, LRSpillOffset));
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fetchLR = false;
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if (fetchLR) {
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int Offset = MFI->getObjectOffset(XFI->getLRSpillSlot());
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SpillList.push_back(std::pair<int,unsigned>(Offset, XCore::LR));
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}
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if (fetchFP)
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SpillList.push_back(std::pair<unsigned, int>(FramePtr, FPSpillOffset));
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if (fetchLR)
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SpillList.push_back(std::pair<unsigned, int>(XCore::LR, LRSpillOffset));
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if (fetchFP) {
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int Offset = MFI->getObjectOffset(XFI->getFPSpillSlot());
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SpillList.push_back(std::pair<int,unsigned>(Offset, FramePtr));
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}
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std::sort(SpillList.begin(), SpillList.end());
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}
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/// Creates an ordered list of EH info register 'spills'.
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/// These slots are only used by the unwinder and calls to llvm.eh.return().
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/// Registers are ordered according to their frame offset.
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/// As offsets are negative, the largest offsets will be first.
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static void GetEHSpillList(SmallVectorImpl<std::pair<int,unsigned> > &SpillList,
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MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
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const TargetLowering *TL) {
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assert(XFI->hasEHSpillSlot() && "There are no EH register spill slots");
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const int* EHSlot = XFI->getEHSpillSlot();
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SpillList.push_back(
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std::pair<int,unsigned>(MFI->getObjectOffset(EHSlot[0]),
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TL->getExceptionPointerRegister()));
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SpillList.push_back(
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std::pair<int,unsigned>(MFI->getObjectOffset(EHSlot[1]),
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TL->getExceptionSelectorRegister()));
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std::sort(SpillList.begin(), SpillList.end());
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}
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/// Restore clobbered registers with their spill slot value.
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/// The SP will be adjusted at the same time, thus the SpillList must be ordered
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/// with the largest (negative) offsets first.
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static void
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RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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DebugLoc dl, const TargetInstrInfo &TII, int &RemainingAdj,
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SmallVectorImpl<std::pair<int,unsigned> > &SpillList) {
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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unsigned SpilledReg = SpillList[i].second;
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int SpillOffset = SpillList[i].first;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
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int Offset = RemainingAdj - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpilledReg).addImm(Offset);
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}
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}
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//===----------------------------------------------------------------------===//
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// XCoreFrameLowering:
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@ -194,11 +234,13 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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// If necessary, save LR and FP to the stack, as we EXTSP.
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SmallVector<std::pair<unsigned,int>,2> SpillList;
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, saveLR, FP);
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// We want the nearest (negative) offsets first, so reverse list.
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std::reverse(SpillList.begin(),SpillList.end());
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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unsigned SpillReg = SpillList[i].first;
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int SpillOffset = SpillList[i].second;
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unsigned SpillReg = SpillList[i].second;
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int SpillOffset = SpillList[i].first;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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@ -239,6 +281,19 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, Offset, SpillLabel);
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}
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if (XFI->hasEHSpillSlot()) {
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// The unwinder requires stack slot & CFI offsets for the exception info.
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// We do not save/spill these registers.
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
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assert(SpillList.size()==2 && "Unexpected SpillList size");
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
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MRI->getDwarfRegNum(SpillList[0].second,true),
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SpillList[0].first, NULL);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
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MRI->getDwarfRegNum(SpillList[1].second,true),
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SpillList[1].first, NULL);
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}
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}
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}
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@ -252,7 +307,19 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned RetOpcode = MBBI->getOpcode();
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// Work out frame sizes.
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// We will adjust the SP in stages towards the final FrameSize.
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int RemainingAdj = MFI->getStackSize();
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assert(RemainingAdj%4 == 0 && "Misaligned frame size");
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RemainingAdj /= 4;
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if (RetOpcode == XCore::EH_RETURN) {
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// 'Restore' the exception info the unwinder has placed into the stack slots.
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
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RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
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// Return to the landing pad.
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unsigned EhStackReg = MBBI->getOperand(0).getReg();
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unsigned EhHandlerReg = MBBI->getOperand(1).getReg();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
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@ -261,12 +328,6 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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return;
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}
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// Work out frame sizes.
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// We will adjust the SP in stages towards the final FrameSize.
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int RemainingAdj = MFI->getStackSize();
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assert(RemainingAdj%4 == 0 && "Misaligned frame size");
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RemainingAdj /= 4;
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bool restoreLR = XFI->hasLRSpillSlot();
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bool UseRETSP = restoreLR && RemainingAdj
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&& (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
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@ -278,20 +339,9 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
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// If necessary, restore LR and FP from the stack, as we EXTSP.
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SmallVector<std::pair<unsigned,int>,2> SpillList;
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, restoreLR, FP);
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unsigned i = SpillList.size();
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while (i--) {
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unsigned SpilledReg = SpillList[i].first;
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int SpillOffset = SpillList[i].second;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
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int Offset = RemainingAdj - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpilledReg).addImm(Offset);
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}
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RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
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if (RemainingAdj) {
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// Complete all but one of the remaining Stack adjustments.
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@ -442,25 +492,32 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
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// If we need to extend the stack it is more efficient to use entsp / retsp.
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// We force the LR to be saved so these instructions are used.
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if (!LRUsed && !MF.getFunction()->isVarArg() &&
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MF.getFrameInfo()->estimateStackSize(MF))
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LRUsed = true;
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// We will be spilling all callee saved registers in case of unwinding.
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if (MF.getMMI().callsUnwindInit())
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// If we need to extend the stack it is more efficient to use entsp / retsp.
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// We force the LR to be saved so these instructions are used.
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LRUsed = true;
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// We will handling LR in the prologue/epilogue
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// and space on the stack ourselves.
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if (MF.getMMI().callsUnwindInit() || MF.getMMI().callsEHReturn()) {
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// The unwinder expects to find spill slots for the exception info regs R0
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// & R1. These are used during llvm.eh.return() to 'restore' the exception
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// info. N.B. we do not spill or restore R0, R1 during normal operation.
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XFI->createEHSpillSlot(MF);
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// As we will have a stack, we force the LR to be saved.
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LRUsed = true;
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}
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if (LRUsed) {
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// We will handle the LR in the prologue/epilogue
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// and allocate space on the stack ourselves.
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MF.getRegInfo().setPhysRegUnused(XCore::LR);
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XFI->createLRSpillSlot(MF);
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}
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// A callee save register is used to hold the FP.
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// This needs saving / restoring in the epilogue / prologue.
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if (hasFP(MF))
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// A callee save register is used to hold the FP.
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// This needs saving / restoring in the epilogue / prologue.
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XFI->createFPSpillSlot(MF);
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}
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@ -58,3 +58,15 @@ int XCoreFunctionInfo::createFPSpillSlot(MachineFunction &MF) {
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return FPSpillSlot;
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}
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const int* XCoreFunctionInfo::createEHSpillSlot(MachineFunction &MF) {
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if (EHSpillSlotSet) {
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return EHSpillSlot;
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}
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const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
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MachineFrameInfo *MFI = MF.getFrameInfo();
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EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
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EHSpillSlot[1] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
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EHSpillSlotSet = true;
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return EHSpillSlot;
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}
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@ -31,6 +31,8 @@ class XCoreFunctionInfo : public MachineFunctionInfo {
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int LRSpillSlot;
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bool FPSpillSlotSet;
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int FPSpillSlot;
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bool EHSpillSlotSet;
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int EHSpillSlot[2];
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int VarArgsFrameIndex;
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mutable int CachedEStackSize;
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std::vector<std::pair<MCSymbol*, CalleeSavedInfo> > SpillLabels;
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@ -38,17 +40,15 @@ class XCoreFunctionInfo : public MachineFunctionInfo {
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public:
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XCoreFunctionInfo() :
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LRSpillSlotSet(false),
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LRSpillSlot(0),
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FPSpillSlotSet(false),
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FPSpillSlot(0),
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EHSpillSlotSet(false),
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VarArgsFrameIndex(0),
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CachedEStackSize(-1) {}
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explicit XCoreFunctionInfo(MachineFunction &MF) :
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LRSpillSlotSet(false),
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LRSpillSlot(0),
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FPSpillSlotSet(false),
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FPSpillSlot(0),
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EHSpillSlotSet(false),
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VarArgsFrameIndex(0),
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CachedEStackSize(-1) {}
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@ -60,17 +60,24 @@ public:
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int createLRSpillSlot(MachineFunction &MF);
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bool hasLRSpillSlot() { return LRSpillSlotSet; }
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int getLRSpillSlot() const {
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assert(LRSpillSlotSet && "LR Spill slot no set");
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assert(LRSpillSlotSet && "LR Spill slot not set");
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return LRSpillSlot;
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}
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int createFPSpillSlot(MachineFunction &MF);
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bool hasFPSpillSlot() { return FPSpillSlotSet; }
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int getFPSpillSlot() const {
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assert(FPSpillSlotSet && "FP Spill slot no set");
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assert(FPSpillSlotSet && "FP Spill slot not set");
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return FPSpillSlot;
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}
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const int* createEHSpillSlot(MachineFunction &MF);
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bool hasEHSpillSlot() { return EHSpillSlotSet; }
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const int* getEHSpillSlot() const {
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assert(EHSpillSlotSet && "EH Spill slot not set");
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return EHSpillSlot;
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}
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bool isLargeFrame(const MachineFunction &MF) const;
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std::vector<std::pair<MCSymbol*, CalleeSavedInfo> > &getSpillLabels() {
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@ -200,7 +200,7 @@ bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
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const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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// The callee saved registers LR & FP are explicitly handled during
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// emitPrologue & emitEpilogue and releated functions.
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// emitPrologue & emitEpilogue and related functions.
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static const uint16_t CalleeSavedRegs[] = {
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XCore::R4, XCore::R5, XCore::R6, XCore::R7,
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XCore::R8, XCore::R9, XCore::R10,
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@ -77,11 +77,18 @@ entry:
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define i8* @EH0(i32 %offset, i8* %handler) {
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entry:
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; CHECK-LABEL: EH0
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; CHECK: ldc r2, 0
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; CHECK: entsp 2
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; CHECK: .cfi_def_cfa_offset 8
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; CHECK: .cfi_offset 15, 0
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; CHECK: .cfi_offset 1, -8
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; CHECK: .cfi_offset 0, -4
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; CHECK: ldc r2, 8
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; CHECK-NEXT: ldaw r3, sp[0]
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; CHECK-NEXT: add r2, r3, r2
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; CHECK-NEXT: add r2, r2, r0
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; CHECK-NEXT: mov r3, r1
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; CHECK-NEXT: ldw r1, sp[0]
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; CHECK-NEXT: ldw r0, sp[1]
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; CHECK-NEXT: set sp, r2
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; CHECK-NEXT: bau r3
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call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
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@ -92,19 +99,27 @@ declare void @foo(...)
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define i8* @EH1(i32 %offset, i8* %handler) {
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entry:
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; CHECK-LABEL: EH1
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; CHECK: entsp 3
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; CHECK: stw r4, sp[2]
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; CHECK: stw r5, sp[1]
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; CHECK: entsp 5
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; CHECK: .cfi_def_cfa_offset 20
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; CHECK: .cfi_offset 15, 0
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; CHECK: .cfi_offset 1, -16
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; CHECK: .cfi_offset 0, -12
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; CHECK: stw r4, sp[4]
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; CHECK: .cfi_offset 4, -4
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; CHECK: stw r5, sp[3]
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; CHECK: .cfi_offset 5, -8
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; CHECK: mov r4, r1
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: ldc r0, 12
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; CHECK-NEXT: ldc r0, 20
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; CHECK-NEXT: ldaw r1, sp[0]
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; CHECK-NEXT: add r0, r1, r0
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; CHECK-NEXT: add r2, r0, r5
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; CHECK-NEXT: mov r3, r4
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; CHECK-NEXT: ldw r5, sp[1]
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; CHECK-NEXT: ldw r4, sp[2]
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; CHECK-NEXT: ldw r5, sp[3]
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; CHECK-NEXT: ldw r4, sp[4]
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; CHECK-NEXT: ldw r1, sp[1]
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; CHECK-NEXT: ldw r0, sp[2]
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; CHECK-NEXT: set sp, r2
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; CHECK-NEXT: bau r3
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call void (...)* @foo()
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@ -117,14 +132,16 @@ entry:
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define i8* @EH2(i32 %r0, i32 %r1, i32 %r2, i32 %r3) {
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entry:
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; CHECK-LABEL: EH2
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; CHECK: entsp 1
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; CHECK: entsp 3
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; CHECK: bl foo
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; CHECK-NEXT: ldw r0, dp[offset]
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; CHECK-NEXT: ldc r1, 4
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; CHECK-NEXT: ldc r1, 12
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; CHECK-NEXT: ldaw r2, sp[0]
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; CHECK-NEXT: add r1, r2, r1
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; CHECK-NEXT: add r2, r1, r0
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; CHECK-NEXT: ldaw r3, dp[handler]
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; CHECK-NEXT: ldw r1, sp[1]
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; CHECK-NEXT: ldw r0, sp[2]
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; CHECK-NEXT: set sp, r2
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; CHECK-NEXT: bau r3
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call void (...)* @foo()
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@ -134,96 +151,213 @@ entry:
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}
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; FP: spill FP+SR+R4:9 = entsp 2 + 6
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; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
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; But we dont actually spill or restore R0:1
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; CHECKFP-LABEL: Unwind0:
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; CHECKFP: entsp 8
|
||||
; CHECKFP: entsp 10
|
||||
; CHECKFP: stw r10, sp[1]
|
||||
; CHECKFP: ldaw r10, sp[0]
|
||||
; CHECKFP: stw r4, r10[7]
|
||||
; CHECKFP: stw r5, r10[6]
|
||||
; CHECKFP: stw r6, r10[5]
|
||||
; CHECKFP: stw r7, r10[4]
|
||||
; CHECKFP: stw r8, r10[3]
|
||||
; CHECKFP: stw r9, r10[2]
|
||||
; CHECKFP: ldw r9, r10[2]
|
||||
; CHECKFP: ldw r8, r10[3]
|
||||
; CHECKFP: ldw r7, r10[4]
|
||||
; CHECKFP: ldw r6, r10[5]
|
||||
; CHECKFP: ldw r5, r10[6]
|
||||
; CHECKFP: ldw r4, r10[7]
|
||||
; CHECKFP: stw r4, r10[9]
|
||||
; CHECKFP: stw r5, r10[8]
|
||||
; CHECKFP: stw r6, r10[7]
|
||||
; CHECKFP: stw r7, r10[6]
|
||||
; CHECKFP: stw r8, r10[5]
|
||||
; CHECKFP: stw r9, r10[4]
|
||||
; CHECKFP: ldw r9, r10[4]
|
||||
; CHECKFP: ldw r8, r10[5]
|
||||
; CHECKFP: ldw r7, r10[6]
|
||||
; CHECKFP: ldw r6, r10[7]
|
||||
; CHECKFP: ldw r5, r10[8]
|
||||
; CHECKFP: ldw r4, r10[9]
|
||||
; CHECKFP: set sp, r10
|
||||
; CHECKFP: ldw r10, sp[1]
|
||||
; CHECKFP: retsp 8
|
||||
; CHECKFP: retsp 10
|
||||
;
|
||||
; !FP: spill R4:10 = entsp 7
|
||||
; !FP: spill R0:1+R4:10 = entsp 2+7
|
||||
; But we dont actually spill or restore R0:1
|
||||
; CHECK-LABEL: Unwind0:
|
||||
; CHECK: entsp 7
|
||||
; CHECK: stw r4, sp[6]
|
||||
; CHECK: stw r5, sp[5]
|
||||
; CHECK: stw r6, sp[4]
|
||||
; CHECK: stw r7, sp[3]
|
||||
; CHECK: stw r8, sp[2]
|
||||
; CHECK: stw r9, sp[1]
|
||||
; CHECK: stw r10, sp[0]
|
||||
; CHECK: ldw r10, sp[0]
|
||||
; CHECK: ldw r9, sp[1]
|
||||
; CHECK: ldw r8, sp[2]
|
||||
; CHECK: ldw r7, sp[3]
|
||||
; CHECK: ldw r6, sp[4]
|
||||
; CHECK: ldw r5, sp[5]
|
||||
; CHECK: ldw r4, sp[6]
|
||||
; CHECK: retsp 7
|
||||
; CHECK: entsp 9
|
||||
; CHECK: stw r4, sp[8]
|
||||
; CHECK: stw r5, sp[7]
|
||||
; CHECK: stw r6, sp[6]
|
||||
; CHECK: stw r7, sp[5]
|
||||
; CHECK: stw r8, sp[4]
|
||||
; CHECK: stw r9, sp[3]
|
||||
; CHECK: stw r10, sp[2]
|
||||
; CHECK: ldw r10, sp[2]
|
||||
; CHECK: ldw r9, sp[3]
|
||||
; CHECK: ldw r8, sp[4]
|
||||
; CHECK: ldw r7, sp[5]
|
||||
; CHECK: ldw r6, sp[6]
|
||||
; CHECK: ldw r5, sp[7]
|
||||
; CHECK: ldw r4, sp[8]
|
||||
; CHECK: retsp 9
|
||||
define void @Unwind0() {
|
||||
call void @llvm.eh.unwind.init()
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; FP: spill FP+SR+R4:9+LR = entsp 2 + 6 + extsp 1
|
||||
; FP: spill FP+SR+R0:1+R4:9+LR = entsp 2+2+6 + extsp 1
|
||||
; But we dont actually spill or restore R0:1
|
||||
; CHECKFP-LABEL: Unwind1:
|
||||
; CHECKFP: entsp 8
|
||||
; CHECKFP: entsp 10
|
||||
; CHECKFP: stw r10, sp[1]
|
||||
; CHECKFP: ldaw r10, sp[0]
|
||||
; CHECKFP: stw r4, r10[7]
|
||||
; CHECKFP: stw r5, r10[6]
|
||||
; CHECKFP: stw r6, r10[5]
|
||||
; CHECKFP: stw r7, r10[4]
|
||||
; CHECKFP: stw r8, r10[3]
|
||||
; CHECKFP: stw r9, r10[2]
|
||||
; CHECKFP: stw r4, r10[9]
|
||||
; CHECKFP: stw r5, r10[8]
|
||||
; CHECKFP: stw r6, r10[7]
|
||||
; CHECKFP: stw r7, r10[6]
|
||||
; CHECKFP: stw r8, r10[5]
|
||||
; CHECKFP: stw r9, r10[4]
|
||||
; CHECKFP: extsp 1
|
||||
; CHECKFP: bl foo
|
||||
; CHECKFP: ldaw sp, sp[1]
|
||||
; CHECKFP: ldw r9, r10[2]
|
||||
; CHECKFP: ldw r8, r10[3]
|
||||
; CHECKFP: ldw r7, r10[4]
|
||||
; CHECKFP: ldw r6, r10[5]
|
||||
; CHECKFP: ldw r5, r10[6]
|
||||
; CHECKFP: ldw r4, r10[7]
|
||||
; CHECKFP: ldw r9, r10[4]
|
||||
; CHECKFP: ldw r8, r10[5]
|
||||
; CHECKFP: ldw r7, r10[6]
|
||||
; CHECKFP: ldw r6, r10[7]
|
||||
; CHECKFP: ldw r5, r10[8]
|
||||
; CHECKFP: ldw r4, r10[9]
|
||||
; CHECKFP: set sp, r10
|
||||
; CHECKFP: ldw r10, sp[1]
|
||||
; CHECKFP: retsp 8
|
||||
; CHECKFP: retsp 10
|
||||
;
|
||||
; !FP: spill R4:10+LR = entsp 7 + 1
|
||||
; !FP: spill R0:1+R4:10+LR = entsp 2+7+1
|
||||
; But we dont actually spill or restore R0:1
|
||||
; CHECK-LABEL: Unwind1:
|
||||
; CHECK: entsp 8
|
||||
; CHECK: stw r4, sp[7]
|
||||
; CHECK: stw r5, sp[6]
|
||||
; CHECK: stw r6, sp[5]
|
||||
; CHECK: stw r7, sp[4]
|
||||
; CHECK: stw r8, sp[3]
|
||||
; CHECK: stw r9, sp[2]
|
||||
; CHECK: stw r10, sp[1]
|
||||
; CHECK: entsp 10
|
||||
; CHECK: stw r4, sp[9]
|
||||
; CHECK: stw r5, sp[8]
|
||||
; CHECK: stw r6, sp[7]
|
||||
; CHECK: stw r7, sp[6]
|
||||
; CHECK: stw r8, sp[5]
|
||||
; CHECK: stw r9, sp[4]
|
||||
; CHECK: stw r10, sp[3]
|
||||
; CHECK: bl foo
|
||||
; CHECK: ldw r10, sp[1]
|
||||
; CHECK: ldw r9, sp[2]
|
||||
; CHECK: ldw r8, sp[3]
|
||||
; CHECK: ldw r7, sp[4]
|
||||
; CHECK: ldw r6, sp[5]
|
||||
; CHECK: ldw r5, sp[6]
|
||||
; CHECK: ldw r4, sp[7]
|
||||
; CHECK: retsp 8
|
||||
; CHECK: ldw r10, sp[3]
|
||||
; CHECK: ldw r9, sp[4]
|
||||
; CHECK: ldw r8, sp[5]
|
||||
; CHECK: ldw r7, sp[6]
|
||||
; CHECK: ldw r6, sp[7]
|
||||
; CHECK: ldw r5, sp[8]
|
||||
; CHECK: ldw r4, sp[9]
|
||||
; CHECK: retsp 10
|
||||
define void @Unwind1() {
|
||||
call void (...)* @foo()
|
||||
call void @llvm.eh.unwind.init()
|
||||
ret void
|
||||
}
|
||||
|
||||
; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
|
||||
; We dont spill R0:1
|
||||
; We only restore R0:1 during eh.return
|
||||
; CHECKFP-LABEL: UnwindEH:
|
||||
; CHECKFP: entsp 10
|
||||
; CHECKFP: .cfi_def_cfa_offset 40
|
||||
; CHECKFP: .cfi_offset 15, 0
|
||||
; CHECKFP: stw r10, sp[1]
|
||||
; CHECKFP: .cfi_offset 10, -36
|
||||
; CHECKFP: ldaw r10, sp[0]
|
||||
; CHECKFP: .cfi_def_cfa_register 10
|
||||
; CHECKFP: .cfi_offset 1, -32
|
||||
; CHECKFP: .cfi_offset 0, -28
|
||||
; CHECKFP: stw r4, r10[9]
|
||||
; CHECKFP: .cfi_offset 4, -4
|
||||
; CHECKFP: stw r5, r10[8]
|
||||
; CHECKFP: .cfi_offset 5, -8
|
||||
; CHECKFP: stw r6, r10[7]
|
||||
; CHECKFP: .cfi_offset 6, -12
|
||||
; CHECKFP: stw r7, r10[6]
|
||||
; CHECKFP: .cfi_offset 7, -16
|
||||
; CHECKFP: stw r8, r10[5]
|
||||
; CHECKFP: .cfi_offset 8, -20
|
||||
; CHECKFP: stw r9, r10[4]
|
||||
; CHECKFP: .cfi_offset 9, -24
|
||||
; CHECKFP: bt r0, .LBB{{[0-9_]+}}
|
||||
; CHECKFP: ldw r9, r10[4]
|
||||
; CHECKFP-NEXT: ldw r8, r10[5]
|
||||
; CHECKFP-NEXT: ldw r7, r10[6]
|
||||
; CHECKFP-NEXT: ldw r6, r10[7]
|
||||
; CHECKFP-NEXT: ldw r5, r10[8]
|
||||
; CHECKFP-NEXT: ldw r4, r10[9]
|
||||
; CHECKFP-NEXT: set sp, r10
|
||||
; CHECKFP-NEXT: ldw r10, sp[1]
|
||||
; CHECKFP-NEXT: retsp 10
|
||||
; CHECKFP: .LBB{{[0-9_]+}}
|
||||
; CHECKFP-NEXT: ldc r2, 40
|
||||
; CHECKFP-NEXT: add r2, r10, r2
|
||||
; CHECKFP-NEXT: add r0, r2, r0
|
||||
; CHECKFP-NEXT: mov r3, r1
|
||||
; CHECKFP-NEXT: mov r2, r0
|
||||
; CHECKFP-NEXT: ldw r9, r10[4]
|
||||
; CHECKFP-NEXT: ldw r8, r10[5]
|
||||
; CHECKFP-NEXT: ldw r7, r10[6]
|
||||
; CHECKFP-NEXT: ldw r6, r10[7]
|
||||
; CHECKFP-NEXT: ldw r5, r10[8]
|
||||
; CHECKFP-NEXT: ldw r4, r10[9]
|
||||
; CHECKFP-NEXT: ldw r1, sp[2]
|
||||
; CHECKFP-NEXT: ldw r0, sp[3]
|
||||
; CHECKFP-NEXT: set sp, r2
|
||||
; CHECKFP-NEXT: bau r3
|
||||
;
|
||||
; !FP: spill R0:1+R4:10 = entsp 2+7
|
||||
; We dont spill R0:1
|
||||
; We only restore R0:1 during eh.return
|
||||
; CHECK-LABEL: UnwindEH:
|
||||
; CHECK: entsp 9
|
||||
; CHECK: .cfi_def_cfa_offset 36
|
||||
; CHECK: .cfi_offset 15, 0
|
||||
; CHECK: .cfi_offset 1, -36
|
||||
; CHECK: .cfi_offset 0, -32
|
||||
; CHECK: stw r4, sp[8]
|
||||
; CHECK: .cfi_offset 4, -4
|
||||
; CHECK: stw r5, sp[7]
|
||||
; CHECK: .cfi_offset 5, -8
|
||||
; CHECK: stw r6, sp[6]
|
||||
; CHECK: .cfi_offset 6, -12
|
||||
; CHECK: stw r7, sp[5]
|
||||
; CHECK: .cfi_offset 7, -16
|
||||
; CHECK: stw r8, sp[4]
|
||||
; CHECK: .cfi_offset 8, -20
|
||||
; CHECK: stw r9, sp[3]
|
||||
; CHECK: .cfi_offset 9, -24
|
||||
; CHECK: stw r10, sp[2]
|
||||
; CHECK: .cfi_offset 10, -28
|
||||
; CHECK: bt r0, .LBB{{[0-9_]+}}
|
||||
; CHECK: ldw r10, sp[2]
|
||||
; CHECK-NEXT: ldw r9, sp[3]
|
||||
; CHECK-NEXT: ldw r8, sp[4]
|
||||
; CHECK-NEXT: ldw r7, sp[5]
|
||||
; CHECK-NEXT: ldw r6, sp[6]
|
||||
; CHECK-NEXT: ldw r5, sp[7]
|
||||
; CHECK-NEXT: ldw r4, sp[8]
|
||||
; CHECK-NEXT: retsp 9
|
||||
; CHECK: .LBB{{[0-9_]+}}
|
||||
; CHECK-NEXT: ldc r2, 36
|
||||
; CHECK-NEXT: ldaw r3, sp[0]
|
||||
; CHECK-NEXT: add r2, r3, r2
|
||||
; CHECK-NEXT: add r0, r2, r0
|
||||
; CHECK-NEXT: mov r3, r1
|
||||
; CHECK-NEXT: mov r2, r0
|
||||
; CHECK-NEXT: ldw r10, sp[2]
|
||||
; CHECK-NEXT: ldw r9, sp[3]
|
||||
; CHECK-NEXT: ldw r8, sp[4]
|
||||
; CHECK-NEXT: ldw r7, sp[5]
|
||||
; CHECK-NEXT: ldw r6, sp[6]
|
||||
; CHECK-NEXT: ldw r5, sp[7]
|
||||
; CHECK-NEXT: ldw r4, sp[8]
|
||||
; CHECK-NEXT: ldw r1, sp[0]
|
||||
; CHECK-NEXT: ldw r0, sp[1]
|
||||
; CHECK-NEXT: set sp, r2
|
||||
; CHECK-NEXT: bau r3
|
||||
define void @UnwindEH(i32 %offset, i8* %handler) {
|
||||
call void @llvm.eh.unwind.init()
|
||||
%cmp = icmp eq i32 %offset, 0
|
||||
br i1 %cmp, label %normal, label %eh
|
||||
eh:
|
||||
call void @llvm.eh.return.i32(i32 %offset, i8* %handler)
|
||||
unreachable
|
||||
normal:
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user