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[Sparc] Add initial implementation of disassembler for sparc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
ba7548302b
commit
9429f47d83
@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td)
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tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter)
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tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
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@ -32,3 +33,4 @@ add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(InstPrinter)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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12
lib/Target/Sparc/Disassembler/CMakeLists.txt
Normal file
12
lib/Target/Sparc/Disassembler/CMakeLists.txt
Normal file
@ -0,0 +1,12 @@
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add_llvm_library(LLVMSparcDisassembler
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SparcDisassembler.cpp
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)
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# workaround for hanging compilation on MSVC9 and 10
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if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500
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OR MSVC_VERSION EQUAL 1600 )
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set_property(
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SOURCE SparcDisassembler.cpp
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PROPERTY COMPILE_FLAGS "/Od"
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)
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endif()
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23
lib/Target/Sparc/Disassembler/LLVMBuild.txt
Normal file
23
lib/Target/Sparc/Disassembler/LLVMBuild.txt
Normal file
@ -0,0 +1,23 @@
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;===- ./lib/Target/Sparc/Disassembler/LLVMBuild.txt ------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[component_0]
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type = Library
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name = SparcDisassembler
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parent = Sparc
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required_libraries = MC Support SparcInfo
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add_to_library_groups = Sparc
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16
lib/Target/Sparc/Disassembler/Makefile
Normal file
16
lib/Target/Sparc/Disassembler/Makefile
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@ -0,0 +1,16 @@
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##===- lib/Target/Sparc/Disassembler/Makefile --------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../../..
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LIBRARYNAME = LLVMSparcDisassembler
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# Hack: we need to include 'main' Sparc target directory to grab private headers
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CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
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include $(LEVEL)/Makefile.common
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228
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
Normal file
228
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
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@ -0,0 +1,228 @@
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//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Sparc Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sparc-disassembler"
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// SparcDisassembler - a disassembler class for Sparc.
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class SparcDisassembler : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
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MCDisassembler(STI), RegInfo(Info)
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{}
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virtual ~SparcDisassembler() {}
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const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
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/// getInstruction - See MCDisassembler.
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virtual DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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private:
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OwningPtr<const MCRegisterInfo> RegInfo;
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};
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}
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namespace llvm {
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extern Target TheSparcTarget, TheSparcV9Target;
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}
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static MCDisassembler *createSparcDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new SparcDisassembler(STI, T.createMCRegInfo(""));
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}
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extern "C" void LLVMInitializeSparcDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
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createSparcDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
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createSparcDisassembler);
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}
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static const unsigned IntRegDecoderTable[] = {
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SP::G0, SP::G1, SP::G2, SP::G3,
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SP::G4, SP::G5, SP::G6, SP::G7,
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SP::O0, SP::O1, SP::O2, SP::O3,
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SP::O4, SP::O5, SP::O6, SP::O7,
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SP::L0, SP::L1, SP::L2, SP::L3,
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SP::L4, SP::L5, SP::L6, SP::L7,
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SP::I0, SP::I1, SP::I2, SP::I3,
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SP::I4, SP::I5, SP::I6, SP::I7 };
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static const unsigned FPRegDecoderTable[] = {
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SP::F0, SP::F1, SP::F2, SP::F3,
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SP::F4, SP::F5, SP::F6, SP::F7,
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SP::F8, SP::F9, SP::F10, SP::F11,
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SP::F12, SP::F13, SP::F14, SP::F15,
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SP::F16, SP::F17, SP::F18, SP::F19,
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SP::F20, SP::F21, SP::F22, SP::F23,
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SP::F24, SP::F25, SP::F26, SP::F27,
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SP::F28, SP::F29, SP::F30, SP::F31 };
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static const unsigned DFPRegDecoderTable[] = {
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SP::D0, SP::D16, SP::D1, SP::D17,
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SP::D2, SP::D18, SP::D3, SP::D19,
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SP::D4, SP::D20, SP::D5, SP::D21,
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SP::D6, SP::D22, SP::D7, SP::D23,
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SP::D8, SP::D24, SP::D9, SP::D25,
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SP::D10, SP::D26, SP::D11, SP::D27,
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SP::D12, SP::D28, SP::D13, SP::D29,
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SP::D14, SP::D30, SP::D15, SP::D31 };
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static const unsigned QFPRegDecoderTable[] = {
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SP::Q0, SP::Q8, -1, -1,
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SP::Q1, SP::Q9, -1, -1,
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SP::Q2, SP::Q10, -1, -1,
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SP::Q3, SP::Q11, -1, -1,
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SP::Q4, SP::Q12, -1, -1,
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SP::Q5, SP::Q13, -1, -1,
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SP::Q6, SP::Q14, -1, -1,
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SP::Q7, SP::Q15, -1, -1 } ;
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = FPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = DFPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = QFPRegDecoderTable[RegNo];
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if (Reg == (unsigned)-1)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return MCDisassembler::Success;
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}
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#include "SparcGenDisassemblerTables.inc"
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/// readInstruction - read four bytes from the MemoryObject
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/// and return 32 bit word.
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static DecodeStatus readInstruction32(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint32_t &insn) {
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uint8_t Bytes[4];
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// We want to read exactly 4 Bytes of data.
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if (region.readBytes(address, 4, Bytes) == -1) {
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size = 0;
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return MCDisassembler::Fail;
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}
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// Encoded as a big-endian 32-bit word in the stream.
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insn = (Bytes[3] << 0) |
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(Bytes[2] << 8) |
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(Bytes[1] << 16) |
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(Bytes[0] << 24);
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return MCDisassembler::Success;
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}
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DecodeStatus
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SparcDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size, Insn);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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@ -16,13 +16,15 @@
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;===------------------------------------------------------------------------===;
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[common]
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subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
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subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
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[component_0]
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type = TargetGroup
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name = Sparc
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parent = Target
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has_asmparser = 1
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has_asmprinter = 1
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has_disassembler = 1
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has_jit = 1
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[component_1]
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@ -14,11 +14,11 @@ TARGET = Sparc
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
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SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \
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SparcGenDAGISel.inc \
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SparcGenDAGISel.inc SparcGenDisassemblerTables.inc \
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SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
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SparcGenCodeEmitter.inc SparcGenMCCodeEmitter.inc
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DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc
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DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
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include $(LEVEL)/Makefile.common
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@ -141,6 +141,7 @@ def : Pat<(i64 imm:$val),
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let Predicates = [Is64Bit] in {
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// Register-register instructions.
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let isCodeGenOnly = 1 in {
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defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
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defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
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defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
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@ -161,26 +162,23 @@ def XNORXrr : F3_1<2, 0b000111,
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defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
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defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
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def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
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def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
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(ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
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"add $rs1, $rs2, $rd, $sym",
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[(set i64:$rd,
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(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
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// Register-immediate instructions.
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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def : Pat<(ctpop i64:$src), (POPCrr $src)>;
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// "LEA" form of add
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let isCodeGenOnly = 1 in
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def LEAX_ADDri : F3_2<2, 0b000000,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"add ${addr:arith}, $dst",
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[(set iPTR:$dst, ADDRri:$addr)]>;
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}
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def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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def : Pat<(ctpop i64:$src), (POPCrr $src)>;
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} // Predicates = [Is64Bit]
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@ -245,7 +243,7 @@ def LDXri : F3_2<3, 0b001011,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"ldx [$addr], $dst",
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[(set i64:$dst, (load ADDRri:$addr))]>;
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let mayLoad = 1 in
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let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
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def TLS_LDXrr : F3_1<3, 0b001011,
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(outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
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"ldx [$addr], $dst, $sym",
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@ -278,24 +276,24 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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// Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
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def LDSWrr : F3_1<3, 0b001011,
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def LDSWrr : F3_1<3, 0b001000,
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(outs I64Regs:$dst), (ins MEMrr:$addr),
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"ldsw [$addr], $dst",
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[(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
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def LDSWri : F3_2<3, 0b001011,
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def LDSWri : F3_2<3, 0b001000,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"ldsw [$addr], $dst",
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[(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
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// 64-bit stores.
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def STXrr : F3_1<3, 0b001110,
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(outs), (ins MEMrr:$addr, I64Regs:$src),
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"stx $src, [$addr]",
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[(store i64:$src, ADDRrr:$addr)]>;
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(outs), (ins MEMrr:$addr, I64Regs:$rd),
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"stx $rd, [$addr]",
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[(store i64:$rd, ADDRrr:$addr)]>;
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def STXri : F3_2<3, 0b001110,
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(outs), (ins MEMri:$addr, I64Regs:$src),
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"stx $src, [$addr]",
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[(store i64:$src, ADDRri:$addr)]>;
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(outs), (ins MEMri:$addr, I64Regs:$rd),
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"stx $rd, [$addr]",
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[(store i64:$rd, ADDRri:$addr)]>;
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// Truncating stores from i64 are identical to the i32 stores.
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def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
|
||||
@ -315,6 +313,15 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// 64-bit Conditionals.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Conditional branch class on %xcc:
|
||||
class XBranchSP<dag ins, string asmstr, list<dag> pattern>
|
||||
: F2_3<0b001, 0b10, (outs), ins, asmstr, pattern> {
|
||||
let isBranch = 1;
|
||||
let isTerminator = 1;
|
||||
let hasDelaySlot = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// Flag-setting instructions like subcc and addcc set both icc and xcc flags.
|
||||
// The icc flags correspond to the 32-bit result, and the xcc are for the
|
||||
@ -326,7 +333,7 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
|
||||
let Predicates = [Is64Bit] in {
|
||||
|
||||
let Uses = [ICC] in
|
||||
def BPXCC : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
|
||||
def BPXCC : XBranchSP<(ins brtarget:$imm22, CCOp:$cond),
|
||||
"b$cond %xcc, $imm22",
|
||||
[(SPbrxcc bb:$imm22, imm:$cond)]>;
|
||||
|
||||
@ -409,7 +416,7 @@ def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
|
||||
|
||||
|
||||
// 64 bit SETHI
|
||||
let Predicates = [Is64Bit] in {
|
||||
let Predicates = [Is64Bit], isCodeGenOnly = 1 in {
|
||||
def SETHIXi : F2_1<0b100,
|
||||
(outs IntRegs:$rd), (ins i64imm:$imm22),
|
||||
"sethi $imm22, $rd",
|
||||
|
||||
@ -12,6 +12,7 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
field bits<32> Inst;
|
||||
|
||||
let Namespace = "SP";
|
||||
let Size = 4;
|
||||
|
||||
bits<2> op;
|
||||
let Inst{31-30} = op; // Top two bits are the 'op' field
|
||||
@ -20,6 +21,9 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
dag InOperandList = ins;
|
||||
let AsmString = asmstr;
|
||||
let Pattern = pattern;
|
||||
|
||||
let DecoderNamespace = "Sparc";
|
||||
field bits<32> SoftFail = 0;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -58,6 +62,27 @@ class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
|
||||
let Inst{28-25} = cond;
|
||||
}
|
||||
|
||||
class F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern>
|
||||
: InstSP<outs, ins, asmstr, pattern> {
|
||||
bit annul;
|
||||
bits<4> cond;
|
||||
bit pred;
|
||||
bits<19> imm19;
|
||||
|
||||
let op = 0; // op = 0
|
||||
|
||||
bit annul = 0; // currently unused
|
||||
let pred = 1; // default is predict taken
|
||||
|
||||
let Inst{29} = annul;
|
||||
let Inst{28-25} = cond;
|
||||
let Inst{24-22} = op2Val;
|
||||
let Inst{21-20} = ccVal;
|
||||
let Inst{19} = pred;
|
||||
let Inst{18-0} = imm19;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Format #3 instruction classes in the Sparc
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -230,24 +230,24 @@ def FCC_O : FCC_VAL<29>; // Ordered
|
||||
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
|
||||
RegisterClass RC, ValueType Ty, Operand immOp> {
|
||||
def rr : F3_1<2, Op3Val,
|
||||
(outs RC:$dst), (ins RC:$b, RC:$c),
|
||||
!strconcat(OpcStr, " $b, $c, $dst"),
|
||||
[(set Ty:$dst, (OpNode Ty:$b, Ty:$c))]>;
|
||||
(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
|
||||
!strconcat(OpcStr, " $rs1, $rs2, $rd"),
|
||||
[(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
|
||||
def ri : F3_2<2, Op3Val,
|
||||
(outs RC:$dst), (ins RC:$b, immOp:$c),
|
||||
!strconcat(OpcStr, " $b, $c, $dst"),
|
||||
[(set Ty:$dst, (OpNode Ty:$b, (Ty simm13:$c)))]>;
|
||||
(outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
|
||||
!strconcat(OpcStr, " $rs1, $simm13, $rd"),
|
||||
[(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
|
||||
}
|
||||
|
||||
/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
|
||||
/// pattern.
|
||||
multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
|
||||
def rr : F3_1<2, Op3Val,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
||||
!strconcat(OpcStr, " $b, $c, $dst"), []>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
||||
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
|
||||
def ri : F3_2<2, Op3Val,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
||||
!strconcat(OpcStr, " $b, $c, $dst"), []>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
|
||||
!strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -488,31 +488,31 @@ let rd = 0, imm22 = 0 in
|
||||
defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
|
||||
|
||||
def ANDNrr : F3_1<2, 0b000101,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
||||
"andn $b, $c, $dst",
|
||||
[(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
||||
"andn $rs1, $rs2, $rd",
|
||||
[(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
|
||||
def ANDNri : F3_2<2, 0b000101,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
||||
"andn $b, $c, $dst", []>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
|
||||
"andn $rs1, $simm13, $rd", []>;
|
||||
|
||||
defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
|
||||
|
||||
def ORNrr : F3_1<2, 0b000110,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
||||
"orn $b, $c, $dst",
|
||||
[(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
||||
"orn $rs1, $rs2, $rd",
|
||||
[(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
|
||||
def ORNri : F3_2<2, 0b000110,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
||||
"orn $b, $c, $dst", []>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
|
||||
"orn $rs1, $simm13, $rd", []>;
|
||||
defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
|
||||
|
||||
def XNORrr : F3_1<2, 0b000111,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
||||
"xnor $b, $c, $dst",
|
||||
[(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
|
||||
"xnor $rs1, $rs2, $rd",
|
||||
[(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
|
||||
def XNORri : F3_2<2, 0b000111,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
|
||||
"xnor $b, $c, $dst", []>;
|
||||
(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
|
||||
"xnor $rs1, $simm13, $rd", []>;
|
||||
|
||||
// Section B.12 - Shift Instructions, p. 107
|
||||
defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
|
||||
@ -545,21 +545,15 @@ let Defs = [ICC] in
|
||||
|
||||
let Defs = [ICC], rd = 0 in {
|
||||
def CMPrr : F3_1<2, 0b010100,
|
||||
(outs), (ins IntRegs:$b, IntRegs:$c),
|
||||
"cmp $b, $c",
|
||||
[(SPcmpicc i32:$b, i32:$c)]>;
|
||||
(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
|
||||
"cmp $rs1, $rs2",
|
||||
[(SPcmpicc i32:$rs1, i32:$rs2)]>;
|
||||
def CMPri : F3_2<2, 0b010100,
|
||||
(outs), (ins IntRegs:$b, i32imm:$c),
|
||||
"cmp $b, $c",
|
||||
[(SPcmpicc i32:$b, (i32 simm13:$c))]>;
|
||||
(outs), (ins IntRegs:$rs1, i32imm:$simm13),
|
||||
"cmp $rs1, $simm13",
|
||||
[(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
|
||||
}
|
||||
|
||||
let Uses = [ICC], Defs = [ICC] in
|
||||
def SUBXCCrr: F3_1<2, 0b011100,
|
||||
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
|
||||
"subxcc $b, $c, $dst", []>;
|
||||
|
||||
|
||||
// Section B.18 - Multiply Instructions, p. 113
|
||||
let Defs = [Y] in {
|
||||
defm UMUL : F3_12np<"umul", 0b001010>;
|
||||
@ -858,7 +852,7 @@ let Defs = [FCC] in {
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions for Thread Local Storage(TLS).
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
|
||||
def TLS_ADDrr : F3_1<2, 0b000000,
|
||||
(outs IntRegs:$rd),
|
||||
(ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
|
||||
@ -882,6 +876,7 @@ let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
|
||||
let op = 1;
|
||||
let Inst{29-0} = disp;
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V9 Instructions
|
||||
|
||||
4
test/MC/Disassembler/Sparc/lit.local.cfg
Normal file
4
test/MC/Disassembler/Sparc/lit.local.cfg
Normal file
@ -0,0 +1,4 @@
|
||||
targets = set(config.root.targets_to_build.split())
|
||||
if not 'Sparc' in targets:
|
||||
config.unsupported = True
|
||||
|
||||
82
test/MC/Disassembler/Sparc/sparc.txt
Normal file
82
test/MC/Disassembler/Sparc/sparc.txt
Normal file
@ -0,0 +1,82 @@
|
||||
# RUN: llvm-mc --disassemble %s -triple=sparc-unknown-linux | FileCheck %s
|
||||
|
||||
# CHECK: add %g0, %g0, %g0
|
||||
0x80 0x00 0x00 0x00
|
||||
|
||||
# CHECK: add %g1, %g2, %g3
|
||||
0x86 0x00 0x40 0x02
|
||||
|
||||
# CHECK: add %o0, %o1, %l0
|
||||
0xa0 0x02 0x00 0x09
|
||||
|
||||
# CHECK: add %o0, 10, %l0
|
||||
0xa0 0x02 0x20 0x0a
|
||||
|
||||
# CHECK: addcc %g1, %g2, %g3
|
||||
0x86 0x80 0x40 0x02
|
||||
|
||||
# CHECK: addxcc %g1, %g2, %g3
|
||||
0x86 0xc0 0x40 0x02
|
||||
|
||||
# CHECK: udiv %g1, %g2, %g3
|
||||
0x86 0x70 0x40 0x02
|
||||
|
||||
# CHECK: sdiv %g1, %g2, %g3
|
||||
0x86 0x78 0x40 0x02
|
||||
|
||||
# CHECK: and %g1, %g2, %g3
|
||||
0x86 0x08 0x40 0x02
|
||||
|
||||
# CHECK: andn %g1, %g2, %g3
|
||||
0x86 0x28 0x40 0x02
|
||||
|
||||
# CHECK: or %g1, %g2, %g3
|
||||
0x86 0x10 0x40 0x02
|
||||
|
||||
# CHECK: orn %g1, %g2, %g3
|
||||
0x86 0x30 0x40 0x02
|
||||
|
||||
# CHECK: xor %g1, %g2, %g3
|
||||
0x86 0x18 0x40 0x02
|
||||
|
||||
# CHECK: xnor %g1, %g2, %g3
|
||||
0x86 0x38 0x40 0x02
|
||||
|
||||
# CHECK: umul %g1, %g2, %g3
|
||||
0x86 0x50 0x40 0x02
|
||||
|
||||
# CHECK: smul %g1, %g2, %g3
|
||||
0x86 0x58 0x40 0x02
|
||||
|
||||
# CHECK: nop
|
||||
0x01 0x00 0x00 0x00
|
||||
|
||||
# CHECK: sethi 10, %l0
|
||||
0x21 0x00 0x00 0x0a
|
||||
|
||||
# CHECK: sll %g1, %g2, %g3
|
||||
0x87 0x28 0x40 0x02
|
||||
|
||||
# CHECK: sll %g1, 31, %g3
|
||||
0x87 0x28 0x60 0x1f
|
||||
|
||||
# CHECK: srl %g1, %g2, %g3
|
||||
0x87 0x30 0x40 0x02
|
||||
|
||||
# CHECK: srl %g1, 31, %g3
|
||||
0x87 0x30 0x60 0x1f
|
||||
|
||||
# CHECK: sra %g1, %g2, %g3
|
||||
0x87 0x38 0x40 0x02
|
||||
|
||||
# CHECK: sra %g1, 31, %g3
|
||||
0x87 0x38 0x60 0x1f
|
||||
|
||||
# CHECK: sub %g1, %g2, %g3
|
||||
0x86 0x20 0x40 0x02
|
||||
|
||||
# CHECK: subcc %g1, %g2, %g3
|
||||
0x86 0xa0 0x40 0x02
|
||||
|
||||
# CHECK: subxcc %g1, %g2, %g3
|
||||
0x86 0xe0 0x40 0x02
|
||||
Loading…
x
Reference in New Issue
Block a user